Digital signal processor and method for prioritized access by multiple core processors to shared device

• US 6,532,507 B1
• Filed: 05/25/2000
• Issued: 03/11/2003
• Est. Priority Date: 05/28/1999
• Status: Active Grant

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Falik, Ohad, Parameswaran, Subramanian
• Primary Examiner(s): THAI, XUAN MARIAN
• Application Number:
  US09/579,258
• Time in Patent Office: 1,020 Days
• Field of Search: 710/22, 710/23, 710/25, 710/28, 710/32, 710/34, 710/35, 710/45, 710/107, 710/113, 710/108, 710/117, 710/118, 710/119, 710/116, 710/124, 710/125, 710/17, 710/58-60, 710/240, 710/200
• US Class Current: 710/107
• CPC Class Codes: G06F 13/161 with latency improvement
• CPC Class Codes: G06F 13/1663 Access to shared memory

Abstract

A system and signal processing method, in which at least two processors have prioritized, shared access to one or more devices connected along a bus. In preferred embodiments, a fast processor is connected along a first bus, a slow processor and shared device are connected along a second bus, and a communication device is connected between the buses. The communication device is configured to provide the fast processor continuous access to the shared device (in response to grant of an access request by the fast processor) for a limited time that is longer than the time required for a single word transfer, but the slow processor must contend with the fast processor for access to the shared device each time after the slow processor completes a word transfer. Preferably, the communication device provides the fast processor continuous access to the shared device for up to a maximum number of word transfers in response to grant of one access request by the fast processor. Preferably, in response to grant of an access request by the fast processor, transfer of a word between the fast processor and a device is allowed, and then the fast processor is provided continuous access to the device for an additional time not less than a predetermined minimum time and not greater than a predetermined maximum time. The prioritized access technique improves the inter-processor data transfer throughput rate without unfairly depriving the slow processor of access to the shared device.

Claims

1. A system, including:

a first bus;

a second bus;

a first processor connected along the first bus, wherein the first processor operates in response to a first clock having a first frequency;

a device connected along the second bus;

a second processor connected along the second bus, wherein the second processor operates in response to a second clock having a second frequency lower than the first frequency, and wherein the second processor is configured to contend for access to the second bus and thus for access to the device connected along the second bus; and

a communication device connected between the first bus and the second bus, wherein the communication device is configured to provide the first processor continuous access to the second bus for a limited time interval in response to grant of a request by the first processor for access to the second bus, a first time is required for a word transfer between the first processor and the device connected along the second bus, the limited time interval is longer than the first time, and the communication device is configured to continue to provide the first processor continuous access to the second bus, after initial transfer of a word is accomplished between the first processor and the device, for an additional time interval that does not exceed a predetermined maximum time.

2. The system of claim 1, wherein the device connected along the second bus is a memory.

3. The system of claim 1, wherein the device connected along the second bus is a peripheral device.

4. The system of claim 1, wherein the predetermined maximum time is a predetermined maximum number of word transfers, where the predetermined maximum number is greater than one.

5. The system of claim 4, wherein the communication device is configured to continue to provide the first processor access to the second bus, after said initial transfer of a word between the first processor and the device, for an additional predetermined time, and

the communication device is configured to continue to provide the first processor access to the second bus, if the first processor initiates a transfer of an additional word between the first processor and the device during the additional predetermined time, until the transfer of the additional word is completed provided that the first processor has not completed the maximum number of word transfers.

6. The system of claim 5, wherein the communication device is configured to release the second bus, thereby causing both the first processor and the second processor to contend for a subsequent access to the second bus, after the first processor has completed the maximum number of word transfers.

7. The system of claim 5, wherein the communication device is configured to release the second bus, thereby causing both the first processor and the second processor to contend for a subsequent access to the second bus, if the first processor fails to initiate a word transfer during said additional predetermined time.

8. The system of claim 5, wherein the additional predetermined time is a predetermined number of cycles of the first clock.

9. The system of claim 1, wherein the system is an integrated circuit, the second processor is a core processor capable of digital signal processing, and the first processor is another core processor.

10. The system of claim 1, wherein the predetermined maximum time is a predetermined number of cycles of the first clock.

11. The system of claim 10, wherein the communication device is configured to release the second bus, thereby causing both the first processor and the second processor to contend for a subsequent access to the second bus, when the predetermined number of cycles of the first clock has elapsed.

12. The system of claim 1, wherein the communication device is configured to continue to provide the first processor access to the second bus, after initial transfer of a word is accomplished between the first processor and the device, for an additional predetermined time, and

the communication device is configured to continue to provide the first processor access to the second bus, if the first processor initiates a transfer of an additional word between the first processor and the device during the additional predetermined time, until the transfer of the additional word is completed, provided that a predetermined number of cycles of the first clock has not elapsed since the grant of the request by the first processor for access to the second bus.

13. The system of claim 1, wherein the predetermined maximum time is a predetermined maximum number of word transfers, or a predetermined number of cycles of the first clock, whichever is less, where the maximum number of word transfers is a number greater than one,

wherein the communication device is configured to continue to provide the first processor access to the second bus, after initial transfer of a word is accomplished between the first processor and the device, for an additional predetermined time, and

the communication device is configured to continue to provide the first processor access to the second bus, if the first processor initiates a transfer of an additional word between the first processor and the device during the additional predetermined time, until the transfer of the additional word is completed, but only if said transfer of the additional word is completed before the first processor has completed the maximum number of word transfers and before the predetermined number of cycles of the first clock has elapsed following said initial transfer of a word between the first processor and the device.

14. The system of claim 1, also including:

a third bus;

a third processor connected along the third bus, wherein the first processor operates in response to a third clock having a third frequency, wherein the third frequency is greater than second frequency; and

a second communication device connected between the second bus and the third bus, wherein the second communication device is configured to provide the third processor continuous access to the second bus for a second limited time interval in response to grant of a request by the third processor for access to the second bus, a third time is required for a word transfer between the third processor and the device connected along the second bus, the second limited time interval is longer than the third time, and the second communication device is configured to continue to provide the third processor continuous access to the second bus, after initial transfer of a word is accomplished between the third processor and the device, for a second additional time interval that does not exceed a second predetermined maximum time.

15. The system of claim 14, wherein the second predetermined maximum time is that required for the system to accomplish a predetermined number of word transfers between the third processor and the device connected along the second bus, where the predetermined number of word transfers is greater than one.

16. The system of claim 14, wherein the second predetermined maximum time is a predetermined number of cycles of the third clock.

17. A method for controlling access by a first processor and a second processor to a shared device, wherein the first processor operates in response to a first clock having a first frequency and the second processor operates in response to a second clock having a frequency lower than the first frequency, the method including the steps of:

(a) in response to grant of a request by the first processor for access to the device, allowing transfer of a word between the first processor and the device, and then providing the first processor continuous access to the device for an additional limited time, wherein the additional limited time is not less than a predetermined minimum time and not greater than a predetermined maximum time; and

(b) in response to grant of a request by the second processor for access to the device, allowing transfer of a word between the second processor and the device, but then requiring the second processor to contend with the first processor for access to the device for a subsequent word transfer.

18. The method of claim 17, wherein the shared device is a peripheral device, and step (a) includes the steps of:

(c) after the first processor accomplishes a word transfer, continuing to provide the first processor access to the peripheral device for an additional interval whose duration is the predetermined minimum time;

(d) if the first processor initiates an additional word transfer during the additional interval, continuing to provide the first processor access to the peripheral device until the additional word transfer is completed; and

(e) repeating steps (c) and (d) until the predetermined maximum time has elapsed.

19. The method of claim 18, wherein the additional interval is a predetermined number of cycles of the first clock.

20. The method of claim 18, wherein step (e) includes the steps of repeating steps (c) and (d) until the first processor has completed a predetermined maximum number of word transfers.

21. The method of claim 18, wherein step (e) includes the steps of repeating steps (c) and (d) until a predetermined number of cycles of the first clock have elapsed.

22. The method of claim 18, wherein step (e) includes the steps of repeating steps (c) and (d) until completion of a predetermined maximum number of word transfers by the first processor or elapse of a predetermined number of cycles of the first clock, whichever occurs first.

23. The method of claim 17, wherein the first processor is connected along a first bus, each of the second processor and the shared device is connected along a second bus, and step (a) includes the steps of:

(c) in response to grant of the request by the first processor, allowing access by the first processor to the second bus to accomplish said transfer of the word and then continuing to provide the first processor access to the second bus for an additional interval whose duration is the predetermined minimum time;

(d) if the first processor initiates an additional word transfer during the additional interval, continuing to provide the first processor access to the second bus until the additional word transfer is completed; and

(e) repeating steps (c) and (d) until the predetermined maximum time has elapsed.

24. The method of claim 23, wherein step (e) includes the steps of repeating steps (c) and (d) until the first processor has completed a predetermined maximum number of word transfers.

25. The method of claim 23, wherein step (e) includes the steps of repeating steps (c) and (d) until a predetermined number of cycles of the first clock have elapsed.

26. The method of claim 17, wherein the shared device is a memory, and step (a) includes the steps of:

(c) after the first processor accomplishes a word transfer, continuing to provide the first processor access to the memory for an additional interval whose duration is the predetermined minimum time;

(d) if the first processor initiates an additional word transfer during the additional interval, continuing to provide the first processor access to the memory until the additional word transfer is completed; and

(e) repeating steps (c) and (d) until the predetermined maximum time has elapsed.

27. The method of claim 26, wherein the additional interval is a predetermined number of cycles of the first clock.

28. The method of claim 26, wherein step (e) includes the steps of repeating steps (c) and (d) until the first processor has completed a predetermined maximum number of word transfers.

29. The method of claim 28, also including the step of:

terminating the continuous access by the first processor to the memory, thereby causing the first processor and the second processor to contend for a subsequent access to the memory, after the first processor has completed the predetermined maximum number of word transfers.

30. The method of claim 28, also including the step of terminating the continuous access by the first processor to the memory, thereby causing both the first processor and the second processor to contend for a subsequent access to the memory, if the first processor fails to initiate a word transfer during any performance of step (a).

31. The method of claim 26, wherein step (e) includes the steps of repeating steps (c) and (d) until a predetermined number of cycles of the first clock have elapsed.

32. A communication device for use in a system capable of performing processing, wherein the system includes at least a first bus and a second bus, a first processor connected along the first bus, a shared device connected along the second bus, and a second processor connected along the second bus, wherein the first processor operates in response to a first clock having a first frequency, the second processor operates in response to a second clock having a second frequency lower than the first frequency, and the second processor is configured to contend for access to the second bus and thus for access to the shared device, said communication device comprising:

a first terminal for coupling the communication device with the first bus;

a second terminal for coupling the communication device with the second bus; and

circuitry, connected between the first terminal and the second terminal, and configured to provide the first processor continuous access to the second bus for a limited time interval in response to grant of a request by the first processor for access to the second bus, and to provide the first processor continuous access to the second bus, after initial transfer of a word is accomplished between the first processor and the shared device, for an additional time interval that does not exceed a predetermined maximum time, wherein a first time is required for a word transfer between the first processor and the shared device, and the limited time interval is longer than the first time.

33. The communication device of claim 32, wherein the predetermined maximum time is a maximum number of word transfers, where the maximum number of word transfers is a predetermined number greater than one.

34. The communication device of claim 33, wherein the circuitry is configured to continue to provide the first processor access to the second bus, after said initial transfer of a word is accomplished between the first processor and the shared device, for an additional predetermined time, and to continue to provide the first processor access to the second bus, if the first processor initiates a transfer of an additional word between the first processor and the shared device during the additional predetermined time, until the transfer of the additional word is completed provided that the first processor has not completed the maximum number of word transfers.

35. The communication device of claim 32, wherein the predetermined maximum time is a predetermined number of cycles of the first clock.