Arbitrating command requests in a parallel multi-threaded processing system

• US 6,532,509 B1
• Filed: 12/22/1999
• Issued: 03/11/2003
• Est. Priority Date: 12/22/1999
• Status: Expired due to Term

• Current Assignee: Sony Corporation Of America (Sony Group Corp.)
• Original Assignee: Intel Corporation
• Inventors: Bernstein, Debra, Wolrich, Gilbert, Wheeler, William, Adiletta, Matthew J.
• Primary Examiner(s): Ray, Gopal C.
• Application Number:
  US09/470,541
• Time in Patent Office: 1,175 Days
• Field of Search: 710/240-244, 710/200, 710/40, 710/107, 710/52, 710/20, 710/7, 710/105, 710/313, 709/231, 709/200, 709/201, 709/217, 709/104, 711/150, 711/151, 711/148, 712/32, 712/36, 370/464
• US Class Current: 710/240
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming

Abstract

A parallel, multi-threaded processor system and technique for arbitrating command requests is described. The system includes a plurality of microengines, a plurality of shared system resources and a global command arbiter. The global command arbiter uses a command request protocol that is based on the shared system resources and command type to grant or deny a microengine command request for a shared resource.

Claims

1. A parallel, multi-threaded processor system, comprising:

a plurality of microengines, each including at least one command register;

a plurality of system resource interface units connected to the microengines, each including at least one commands queue; and

a global command arbiter including a pointer for storing the identity of the last microengine that had a request granted, the global command arbiter connected to each of the microengines and to the system resource interface units for determining whether a particular microengine command request should be granted.

2. The system of claim 1, further comprising a two-command deep FIFO commands register in each microengine.

3. The system of claim 1, wherein the system resource units include at least one of a core controller, a SDRAM controller, a SRAM controller, a PCI bus interface and an FBUS interface.

4. The system of claim 3, further comprising three command queues in at least one of the SDRAM controller, the SRAM controller and the FBUS interface.

5. The system of claim 3, further comprising a high priority queue in at least one of the SDRAM controller and the SRAM controller.

6. The system of claim 3, further comprising a read lock fail queue in the SRAM controller.

7. The system of claim 3, further comprising a single command register in the PCI bus interface.

8. A method for arbitrating command requests for access to shared system resources in a parallel, multi-threaded processor system, comprising:

establishing a command request protocol based on the shared system resources and command types;

selecting a command request from output command queues of a plurality of microengines according to a command priority which is part of the protocol;

granting a microengine command request to a shared system resource destination queue if the protocol is satisfied; and

denying a microengine command request if the protocol is not satisfied.

9. The method of claim 8, further comprising considering a command request of the next highest microengine if all command requests are of equal priority.

10. The method of claim 8, further comprising considering a command request of a lower priority when a microengine command request is denied.

11. The method of claim 8, further comprising giving top priority to a chained SDRAM command request.

12. The method of claim 11, further comprising giving the next highest priority to a SPAN command request.

13. The method of claim 12, further comprising giving the next highest priority to a non-chained SDRAM command request.

14. The method of claim 13, further comprising denying consecutive SDRAM command requests.

15. The method of claim 13, further comprising giving the next highest priority to a FBUS command request.

16. The method of claim 15, further comprising denying consecutive FBUS command requests.

17. The method of claim 15, further comprising giving the lowest priority to a PCI bus command request.

18. An article comprising a computer-readable medium which stores computer executable instructions for arbitrating command requests for shared system resources in a parallel, multi-threaded system, the instructions causing a computer to:

establish a command request protocol based on the shared system resources and command types;

select a command request from output command queues of a plurality of microengines according to a command priority which is part of the protocol;

grant a microengine command request to a shared system resource destination queue if the protocol is satisfied; and

deny a microengine command request if the protocol is not satisfied.

19. The article of claim 18, the instructions further causing a computer to consider a command request of the next highest microengine if all command requests are of equal priority.

20. The article of claim 18, the instructions further causing a computer to consider a command request of a lower priority when a microengine command request is denied.

21. The article of claim 18, the instructions further causing a computer to assign top priority to chained SDRAM command requests.

22. The article of claim 21, the instructions further causing a computer to assign the next highest priority to SRAM command requests.

23. The article of claim 22, the instructions further causing a computer to assign the next highest priority to non-chained SDRAM command requests.

24. The article of claim 23, the instructions further causing a computer to deny consecutive SDRAM command requests.

25. The article of claim 23, the instructions further causing a computer to assign the next highest priority to FBUS command requests.

26. The article of claim 25, the instructions further causing a computer to deny consecutive FBUS command requests.

27. The article of claim 25, the instructions further causing a computer to assign the lowest priority to PCI bus command requests.

28. A method for arbitrating command requests for access to shared system resources, in a parallel, multi-threaded processor system, comprising:

arbitrating command requests of a plurality of microengines based on a command protocol;

granting a command request for transmission to a queue in a system resource;

storing the command in the queue of the system resource;

generating a full status queue signal if there are less than an adequate number of spaces available to store further commands in the queue; and

denying further command requests for storage in that queue if the full status queue signal was generated.

29. The method of claim 28, further comprising establishing a command protocol that gives highest priority to chained SDRAM command requests.

30. The method of claim 29, further comprising establishing the next highest priorities in the order of SRAM command requests, non-chained SDRAM command requests, FBUS command requests and PCI bus command requests.

31. The method of claim 28, further comprising establishing a command protocol that considers a command request of a lower priority when a microengine command request is denied.

32. An article comprising a computer-readable medium which stores computer executable instructions for arbitrating command request for access to shared system resources in a parallel, multi-threaded processor system, the instructions causing a computer to:

arbitrate command requests of a plurality of microengines based on a command protocol;

grant a command request for transmission to a queue in a system resource;

store the command in the queue of the system resource;

a full status queue signal if there are less than an adequate number of spaces available to store further commands in the queue; and

deny further command requests for storage in that queue if the full status queue signal was generated.

33. The article of claim 32, the instructions further causing a computer to establish a command protocol that gives highest priority to chained SDRAM command requests.

34. The article of claim 32, the instructions further causing a computer to establish the next highest priorities in the order of SRAM command requests, non-chained SDRAM command requests, FBUS command requests and PCI bus command requests.

35. The article of claim 32, the instructions further causing a computer to establish a command protocol that considers a command request of a lower priority when a microengine command request is denied.