Data management for multi-bit-per-cell memories

• US 6,532,556 B1
• Filed: 01/27/2000
• Issued: 03/11/2003
• Est. Priority Date: 01/27/2000
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Multi Level Memory Technology
• Inventors: So, Hock Chuen, Wong, Sau Ching
• Primary Examiner(s): Decady; Albert
• Assistant Examiner(s): BRITT, CYNTHIA H
• Application Number:
  US09/492,949
• Time in Patent Office: 1,139 Days
• Field of Search: 714/702,718,719 711/220
• US Class Current: 714/702
• CPC Class Codes: G06F 12/1408 by using cryptography for digital transmission H04L9/00
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 2211/5648 Multilevel memory programming, reading or erasing operations wherein the order or sequence of the operations is relevant
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation

Abstract

A multi-bit-per-cell memory reduces the effect of defects and data errors by scrambling data bits before writing data. The scrambling prevents storage of consecutive bits in the same memory cell. When a memory cell is defective or produces an error, the bits read from the memory cell do not create consecutive bit errors that would be noticeable or uncorrectable. An error or a defect in a multi-bit memory cell causes at most scattered bit errors. Scramblers in multi-bit-per-cell memories can include 1) hardwired lines crossing between an input port and an output port, 2) programmable wiring options, 3) a linear buffer where reads from the buffer use addresses with swapped bits, or 4) a buffer array that switches between incrementing a row address first and incrementing a column address first when accessing memory cells in the buffer array.

Claims

1. A multi-bit-per-cell memory comprising:

an array of memory cells wherein each memory cell stores N bits of information;

a scrambler connected to receive a group of M data bits and provide a set of scrambled N-bit values containing bits from the group, wherein M is an integer greater than N, and bits in each scrambled N-bit value have an order that differs from an order in the group; and

a write circuit coupled to the scrambler and the array, wherein the write circuit writes each scrambled N-bit value from the scrambler into a memory cell associated with the scrambled N-bit value.

2. The memory of claim 1, further comprising:

a read circuit coupled to read the memory cells of the array; and

a descrambler coupled to the read circuit, wherein the descrambler receives a set of N-bit values read from associated memory cells of the array and mixes bits from the N-bit values to reconstruct a group of M data bits.

3. The memory of claim 1, wherein the scrambler is hardwired to receive M bits in an order according to the group, mix the M bits to provide a scrambled M-bit group, and partition the scrambled M-bit group into the scrambled N-bit groups.

4. The memory of claim 3, wherein the scrambler comprises:

an input port that receives the M bits in the order according to the group;

an output port that provides the scrambled M-bit group; and

connections between the input port and the output port that scramble the order of the bits of the M-bit group.

5. The memory of claim 1, wherein the scrambler is programmable to select a mapping according to which the scramble maps the M-bit group to a scrambled M-bit group that is partitioned into the scrambled N-bit groups.

6. The memory of claim 1, wherein:

each bit in the group has a multi-bit address defining a position of the bit in the group; and

the scrambler receives M bits of the group, creates a scrambled M-bit group by reordering each bit of the group according to a new address that results from swapping bits in the multi-bit address, and partitions the scrambled M-bit group into the scrambled N-bit groups.

7. The memory of claim 1, wherein the scrambler comprises:

a buffer array; and

an address control circuit for operation of the buffer array, the address control circuit being operable in a first mode that increments a row address for each bit accessed in the buffer array and a second mode that increments a column address for each bit accessed in the buffer array, wherein

the scrambler provides a scrambled N-bit value by;

sequentially writing bits from the group into the buffer array while operating in one of the first and second modes;

changing mode; and

then

reading N bits from the buffer array.

8. The memory of claim 7, further comprising a read circuit coupled to read the memory cells of the array, wherein the scrambler provides output data by:

sequentially writing bits from the read circuit into the buffer array while operating in one of the first and second modes;

changing mode; and

then

reading the output data from the buffer array.

9. The multi-bit-per-cell memory of claim 1, wherein the scrambled N-bit values are such that no pair of consecutive bits in the group of M data bits are written into the same memory cell.

10. The multi-bit-per-cell memory of claim 1, wherein the group of M data bits contains X-bit data units, and the scrambled N-bit values are such that no two bits from the same X-bit data unit are in the same scrambled N-bit value.

11. The multi-bit-per-cell memory of claim 1, wherein the scrambled N-bit values are such that each set of N bits that are consecutive in the group of M data bits is spread over multiple memory cells when written in the array.

12. A method for writing data to a multi-bit-per-cell memory, comprising:

scrambling data bits from a data stream to create a scrambled data stream, wherein the data stream contains X-bit data values with X being greater than 1;

partitioning the scrambled data stream into a set of N-bit values, wherein N is greater than 1; and

writing each N-bit value in a corresponding memory cell, wherein the scrambling is such that for each X-bit data value in the data stream, no two bits from the X-bit data value are written in the same memory cell.

13. The method of claim 12, wherein circuitry inside an integrated circuit memory device performs the scrambling, partitioning, and writing.

14. The method of claim 12, further comprising:

reading a set of read N-bit values from a set of the memory cells; and

mixing bits from different read N-bit values to generate output data.

15. The method of claim 14, wherein circuitry inside an integrated circuit memory device performs the scrambling, partitioning, writing, reading, and mixing.

16. The method of claim 12, wherein scrambling comprises receiving M bits at an input port that is hardwired to an output port, wherein hardwiring causes an order of bits along the output port to differ from an order of bits along the input port.

17. The method of claim 12, wherein:

each bit in an M-bit group from the data stream has a multi-bit address defining a position of the bit in the data stream; and

scrambling comprises creating a scrambled M-bit group by ordering each bit according to a new address that results from swapping bits in the multi-bit address defining the position of the bit in the data stream.

18. The method of claim 12, wherein scrambling comprises:

sequentially writing bits from the data stream into a buffer while operating in the buffer in a first mode; and

reading bits from the buffer array while operating in the buffer in a second mode, wherein one of the first and second modes increments a row address for each bit accessed in the buffer, and another of the first and second modes increments a column address for each bit accessed in the buffer.

19. A multi-bit-per-cell memory comprising:

an array of memory cells wherein each memory cell stores N bits of data, wherein N is greater than 1;

a scrambler connected to scramble bits of an input M-bit data group to generate a scrambled M-bit group, wherein the scrambled M-bit data group includes multiple scrambled N-bit values; and

a write circuit coupled to the scrambler and the array, wherein the write circuit writes each scrambled N-bit value into a different one of the memory cells of the array.

20. The multi-bit-per-cell memory of claim 19, wherein the scrambled N-bit values are such that no pair of bits that are consecutive in the input M data group are written into the same memory cell.

21. The multi-bit-per-cell memory of claim 19, wherein the input M-bit data group contains X-bit data units, and the scrambled N-bit values are such that no two bits from the same X-bit data unit are in the same scrambled N-bit value.

22. The multi-bit-per-cell memory of claim 19, wherein the scrambled N-bit values are such that storage of each set of N bits that are consecutive in the input M-bit data group is spread over multiple memory cells in the array.