Method for fabricating a MOSFET device
First Claim
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1. A method for fabricating a MOSFET device on a silicon substrate comprising:
- forming field oxide regions to define an active region on the silicon substrate provided;
forming a oxide film on the active region;
forming a polysilicon film on the oxide film;
forming a hard mask pattern defining a gate formation region on the polysilicon film;
forming a sacrificial gate by etching the polysilicon film and the oxide film using the hard mask pattern as an etching mask and thereby exposing regions of the silicon substrate;
forming a thermal oxide film on side walls of the sacrificial gate and the exposed regions of the silicon substrate by a re-oxidation process;
implanting impurity ions having a desired conductivity into the silicon substrate using the sacrificial gate as an ion implant mask to form LDD regions in the silicon substrate;
removing the thermal oxide film;
forming a spacer on the side walls of the sacrificial gate and the hard mask pattern;
implanting impurity ions having a desired conductivity into the silicon substrate using the sacrificial gate and the spacers as an ion implantation mask to form source/drain regions in the silicon substrate;
depositing an interlayer insulating film;
removing a portion of the interlayer insulating film and the hard mask pattern to expose an upper surface of the sacrificial gate;
removing the sacrificial gate, thereby forming a groove and exposing that portion of the silicon substrate that had been disposed under the sacrificial gate;
etching the exposed silicon substrate to remove a desired thickness and form an etched silicon substrate;
forming a sacrificial oxide film of a desired thickness on the etched silicon substrate;
implanting a predetermined quantity of impurity ions having a desired conductivity through the sacrificial oxide film and into the silicon substrate to produce a desired threshold voltage;
removing the sacrificial oxide film to expose portions of the etched silicon substrate;
forming a gate insulating film on the exposed portions of the etched silicon substrate;
depositing a metal film, the thickness of the metal film being sufficient to fill the groove; and
removing a portion of the metal film to expose a surface of the interlayer insulating film and to form a metal gate in the groove above the gate insulating film.
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Abstract
Disclosed is a MOSFET fabrication method capable of forming an ultra shallow junction while ensuring stability in controlling threshold voltage. The disclosed method relies on the use of a sacrificial gate structure to form LDD regions and the addition of side wall spacers to form source/drain regions, followed by the deposition of an interlayer insulating film. The sacrificial gate structure is then removed to form a groove in the interlayer insulating film that exposes a portion of the silicon substrate. A sacrificial oxide is grown on the exposed silicon substrate and impurity ions are implanted through the oxide to adjust the threshold voltage. The sacrificial oxide is then removed and replaced by a high quality gate insulating film. A metal gate electrode is then formed in the groove above the gate insulating film, thereby forming a MOSFET device having a metal gate.
233 Citations
12 Claims
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1. A method for fabricating a MOSFET device on a silicon substrate comprising:
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forming field oxide regions to define an active region on the silicon substrate provided;
forming a oxide film on the active region;
forming a polysilicon film on the oxide film;
forming a hard mask pattern defining a gate formation region on the polysilicon film;
forming a sacrificial gate by etching the polysilicon film and the oxide film using the hard mask pattern as an etching mask and thereby exposing regions of the silicon substrate;
forming a thermal oxide film on side walls of the sacrificial gate and the exposed regions of the silicon substrate by a re-oxidation process;
implanting impurity ions having a desired conductivity into the silicon substrate using the sacrificial gate as an ion implant mask to form LDD regions in the silicon substrate;
removing the thermal oxide film;
forming a spacer on the side walls of the sacrificial gate and the hard mask pattern;
implanting impurity ions having a desired conductivity into the silicon substrate using the sacrificial gate and the spacers as an ion implantation mask to form source/drain regions in the silicon substrate;
depositing an interlayer insulating film;
removing a portion of the interlayer insulating film and the hard mask pattern to expose an upper surface of the sacrificial gate;
removing the sacrificial gate, thereby forming a groove and exposing that portion of the silicon substrate that had been disposed under the sacrificial gate;
etching the exposed silicon substrate to remove a desired thickness and form an etched silicon substrate;
forming a sacrificial oxide film of a desired thickness on the etched silicon substrate;
implanting a predetermined quantity of impurity ions having a desired conductivity through the sacrificial oxide film and into the silicon substrate to produce a desired threshold voltage;
removing the sacrificial oxide film to expose portions of the etched silicon substrate;
forming a gate insulating film on the exposed portions of the etched silicon substrate;
depositing a metal film, the thickness of the metal film being sufficient to fill the groove; and
removing a portion of the metal film to expose a surface of the interlayer insulating film and to form a metal gate in the groove above the gate insulating film. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
further wherein the step of removing a portion of the metal film to expose a surface of the interlayer insulating film comprises a chemical mechanical polishing or etch back process.
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Current AssigneeHynix Semiconductor Incorporated (SK Hynix Inc.)
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Original AssigneeHynix Semiconductor Incorporated (SK Hynix Inc.)
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InventorsKim, Tae Kyun
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Primary Examiner(s)Chaudhuri, Olik
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Assistant Examiner(s)LEE, HSIEN MING
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Application NumberUS09/885,083Time in Patent Office635 DaysField of Search438/197, 438/270-297, 438/299, 438/301, 438/303, 438/595, 438/259, 257/344, 257/330US Class Current438/197CPC Class CodesH01L 21/2652 Through-implantationH01L 21/28167 on single crystalline silic...H01L 29/518 the insulating material con...H01L 29/66537 using a self aligned punch ...H01L 29/66545 using a dummy, i.e. replace...H01L 29/66621 using etching to form a rec...
