Linerless shallow trench isolation method

• US 6,534,379 B1
• Filed: 01/18/2002
• Issued: 03/18/2003
• Est. Priority Date: 03/26/2001
• Status: Expired due to Fees

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Lin, Ming-Ren, Buynoski, Matthew S., Fisher, Philip
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): MAI, ANH D
• Application Number:
  US10/051,698
• Time in Patent Office: 424 Days
• Field of Search: 438/424, 438/427, 438/435
• US Class Current: 438/424
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 21/76283 Lateral isolation by refilling of trenches with dielectric material

Abstract

A method of making a semiconductor device and a method of isolation of active islands on a silicon-on-insulator semiconductor device, comprising the steps of providing a silicon-on-insulator semiconductor wafer having a silicon active layer, a dielectric isolation layer and a silicon substrate, in which the silicon active layer is formed on the dielectric isolation layer and the dielectric isolation layer is formed on the silicon substrate; forming an isolation trench, the isolation trench defining an active island in the silicon active layer; rounding at least one corner in the active island by application of a high RF bias power high density plasma; and filling the isolation trench with a dielectric trench isolation material by application of a low RF bias power high density plasma. In one embodiment, the rounding step comprises application of a HDP under etching conditions, and the filling step comprises application of a HDP under deposition conditions.

Claims

1. A method of isolation of active islands on a silicon-on-insulator semiconductor device, comprising the steps of:

providing a silicon-on-insulator semiconductor wafer having a silicon active layer, a dielectric isolation layer and a silicon substrate, in which the silicon active layer is formed on the dielectric isolation layer and the dielectric isolation layer is formed on the silicon substrate;

forming an isolation trench, the isolation trench defining an active island in the silicon active layer;

rounding at least one corner in the active island by application of a high RF bias power high density plasma; and

filling the isolation trench with a dielectric trench isolation material by application of a low RF bias power high density plasma,

wherein the step of rounding at least one corner is carried out without formation of a bird'"'"'s beak under the active island.

2. The method of claim 1, wherein a shallow trench isolation structure is formed without first forming an oxide trench liner.

3. The method of claim 1, wherein a shallow trench isolation structure is formed without first oxidizing sidewalls in the isolation trench.

4. The method of claim 1, wherein the semiconductor device is annealed at a temperature less than 1100°

C. following the step of filling the trench.

5. The method of claim 1, wherein the high density plasma is electron cyclotron resonance plasma chemical vapor deposition.

6. The method of claim 1, wherein the high density plasma is transformer coupled plasma chemical vapor deposition.

7. The method of claim 1, wherein the step of forming the isolation trench etches through the active silicon layer to the insulating dielectric layer.

8. The method of claim 1, wherein in the step of rounding at least one corner, the plasma gas comprises oxygen and a noble gas.

9. The method of claim 1, wherein in the step of filling, the plasma gas comprises oxygen, silicon and a noble gas.

10. A method of isolation of active islands on a silicon-on-insulator semiconductor device, comprising the steps of:

providing a silicon-on-insulator semiconductor wafer having a silicon active layer, a dielectric isolation layer and a silicon substrate, in which the silicon active layer is formed on the dielectric isolation layer and the dielectric isolation layer is formed on the silicon substrate;

forming an isolation trench by etching through the silicon active layer, the isolation trench defining an active island in the silicon active layer;

rounding at least one upper corner in the active island by application of a high RF bias power high density plasma, under etching conditions; and

filling the isolation trench with a dielectric trench isolation material by application of a low RF bias power high density plasma, under deposition conditions,

wherein the step of rounding at least one corner is carried out without formation of a bird'"'"'s beak under the active island.

11. The method of claim 10, wherein the etching conditions comprise an etch to deposition ratio resulting in etching of silicon from the corners.

12. The method of claim 10, wherein the deposition conditions comprise forming a plasma gas comprising oxygen and at least one gas selected from neon, argon, krypton and xenon, and providing a source of a reactant gas to the plasma.

13. The method of claim 12, wherein the reactant gas comprises silicon.

14. The method of claim 10, wherein the deposition conditions comprise an etch to deposition ratio resulting in deposition of the dielectric trench isolation material in the isolation trench.

15. The method of claim 10, wherein the high density plasma is electron cyclotron resonance plasma chemical vapor deposition.

16. The method of claim 10, wherein the high density plasma is transformer coupled plasma chemical vapor deposition.

17. The method according to claim 10, wherein a shallow trench isolation structure is formed without first forming a sidewall in the isolation trench.

18. A method of isolation of active islands on a silicon-on-insulator semiconductor device, comprising the steps of:

providing a silicon-on-insulator semiconductor wafer having a silicon active layer, a dielectric isolation layer and a silicon substrate, in which the silicon active layer is formed on the dielectric isolation layer and the dielectric isolation layer is formed on the silicon substrate;

forming an isolation trench by etching through the silicon active layer, the isolation trench defining an active island in the silicon active layer;

rounding at least one upper corner in the active island by application of a high RF bias power high density plasma, under etching conditions, to form a shallow trench isolation structure; and

filling the isolation trench with a dielectric trench isolation material by application of a low RF bias power high density plasma, under deposition conditions,

wherein the step of rounding at least one corner is carried out without formation of a bird'"'"'s beak under the active island and the shallow trench isolation structure is formed without first forming a sidewall in the isolation trench.