Salicide method for producing a semiconductor device using silicon/amorphous silicon/metal structure

• US 6,534,390 B1
• Filed: 01/16/2002
• Issued: 03/18/2003
• Est. Priority Date: 01/16/2002
• Status: Expired due to Fees

• Current Assignee: Chartered Semiconductor Manufacturing Incorporated (GlobalFoundries, Inc.)
• Original Assignee: Chartered Semiconductor Manufacturing Incorporated (GlobalFoundries, Inc.)
• Inventors: Chong, Yung Fu, Pey, Kin Leong, Cha, Randall
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): Lee, Hsien Ming
• Application Number:
  US10/050,444
• Time in Patent Office: 426 Days
• Field of Search: 438/592, 438/595, 438/651, 438/652, 438/660, 438/663, 438/682, 438/692, 257/382, 257/383, 257/384, 257/388, 257/412, 257/754
• US Class Current: 438/592
• CPC Class Codes: H01L 21/28052 the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer formed by metal ion implantation H01L21/28044
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/3212 by chemical mechanical polishing [CMP]
• CPC Class Codes: H01L 29/41783 Raised source or drain electrodes self aligned with the gate
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

The present invention provides an improved semiconductor device of a Silicon/Amorphous Silicon/Metal Structure (SASM) and a method of making an improved semiconductor device by a salicide process by using an anneal to form a thick silicide film on shallow source/drain regions and a chemical-mechanical polish (CMP) step is then performed to remove the silicide over the top of the spacers at the gate, thus breaking the continuity of the silicide film extending from the gate to the source drain region.

Claims

1. A method for forming semiconductor device comprising:

providing a substrate;

forming a gate dielectric layer over said substrate;

forming a gate layer over said gate dielectric layer;

forming a cap layer over said gate layer;

creating a lightly doped source/drain region in the substrate, and not under the gate dielectric layer;

forming spacers on the sidewalls of said gate dielectric layer, and said gate layer, and said cap layer to form an intermediate structure;

forming a deep source/drain region in said substrate and under said lightly doped source/drain region;

annealing to activate the dopants;

removing the cap layer;

depositing a silicon film over said intermediate structure;

depositing a metal layer over said silicon film;

forming a silicide layer from the silicon film and the metal layer by using laser irradiation;

subjecting the silicon body to a heat treatment to convert the silicide regions into low-resistivity silicides;

depositing an interlevel dielectric layer over said silicide layer;

chemical-mechanical polish (CMP) said interlevel dielectric layer, said spacers and said silicide to break the continuity of the silicide film to create a source/drain silicide film and a gate silicide film.

2. The method of claim 1, wherein the gate dielectric is made of silicon oxynitride having a thickness between 10 and 150 Å

.

3. The method of claim 1, wherein the gate layer is made of doped poly silicon.

4. The method of claim 1, wherein the cap layer is nitride having a thickness between 500 and 2000 Å

.

5. The method of claim 1, wherein the lightly doped source/drain area is formed by ion implantation.

6. The method of claim 1, wherein the spacer is made of an oxide film having a thickness in the range of 300 and 1500 Å

.

7. The method of claim 1, wherein the spacers are made using anisotropic etch.

8. The method of claim 7, wherein the anisotropic etch used is an oxide dry etch.

9. The method of claim 1, wherein the deep source/drain region is formed by ion implantation.

10. The method of claim 1, wherein after creating the deep source/drain region, an annealing of the intermediate structure is done to activate dopants.

11. The method of claim 1, wherein the removing of the cap layer is done by selective etching.

12. The method of claim 1, wherein the silicon film is amorphous silicon.

13. The method of claim 12, wherein the amorphous silicon is deposited using low-pressure chemical vapor deposition (LPCVD) with silane (SiH4) as the reacting gas.

14. The method of claim 1, wherein the metal layer is one of the following:

a. titanium,

b. cobalt,

c. or nickel.

15. The method of claim 1, wherein the laser irradiation is from a pulsed excimer laser source.

16. The method of claim 1, wherein the laser irradiation is done at about 157 nm to 308 nm.

17. The method of claim 16, wherein the laser irradiation is done at 248 nm.

18. The method of claim 1, wherein the silicide layer is one of the following:

a. titanium silicide,

b. cobalt silicide,

c. or nickel silicid.

19. The method of claim 1, wherein the interlevel dielectric layer is an oxide.

20. The method of claim 1, wherein the silicide layer is formed from a Silicon/Amorphous Silicon/Metal structure.

21. The method of claim 1, wherein the metal layer is deposited using physical vapor deposition.

22. The method of claim 1, wherein the heat treatment can either be a RTA step or subsequent laser irradiation.

23. The method claim of claim 22 wherein the RTA step is in the temperature range from 250 to 900 degrees Centigrade, and has a duration in the range of 5 seconds to 1 hour.

24. The method claim of claim 22 wherein the heat treatment for using laser irradiation has a fluence is in the range of 0.05 to 0.5 J/cm squared, with the number of pulses applied ranging from 1 to 100″

.

25. A method for forming semiconductor device comprising:

providing a substrate;

forming a gate dielectric layer over said substrate;

forming a gate layer over said gate dielectric layer;

forming a cap layer over said gate layer;

forming spacers on the sidewalls of said gate dielectric layer, and said gate layer and said cap layer to form an intermediate structure;

creating a lightly doped source/drain region in the substrate, and not under the gate dielectric layer; and

said cap layer to form an intermediate structure;

forming a deep source/drain region in said substrate and under said lightly doped source/drain region;

removing the cap layer;

depositing a silicon film over said intermediate structure;

depositing a metal layer over said silicon film;

forming a silicide layer from the silicon film and the metal layer by using rapid thermal annealing;

depositing an inter level dielectric layer over said silicide layer;

chemical-mechanical polish (CMP)said inter level dielectric layer, said spacers and said silicide to break the continuity of the silicide film to create a source/drain silicide film and a gate silicide film.

26. The Method of claim 25, wherein the rapid thermal annealing is at temperature range of about 250 to 900 degrees Centigrade;

and duration ranges from 5 seconds to 1 hour.