Semiconductor package having substrate with laser-formed aperture through solder mask layer

• US 6,534,391 B1
• Filed: 08/17/2001
• Issued: 03/18/2003
• Est. Priority Date: 08/17/2001
• Status: Active Grant

• Current Assignee: Amkor Technology Singapore Holding Pte., Ltd. (Amkor Technology Incorporated)
• Original Assignee: Amkor Technology Incorporated
• Inventors: Rusli, Sukianto, Huemoeller, Ronald Patrick
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Dang, Phuc T.
• Application Number:
  US09/932,528
• Time in Patent Office: 578 Days
• Field of Search: 438/106, 438/107, 438/108, 438/110, 438/113, 438/122, 438/124, 438/126, 438/127, 438/612
• US Class Current: 438/612
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48228 the bond pad being disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49894 Materials of the insulating layers or coatings
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01046 Palladium [Pd]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/15173 in a single layer of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 Encapsulation
• CPC Class Codes: H01L 2924/207 Diameter ranges
• CPC Class Codes: H05K 2203/049 Wire bonding
• CPC Class Codes: H05K 3/0035 : of blind holes, i.e. having a metal layer at the bottom
• CPC Class Codes: H05K 3/28 : Applying non-metallic protective coatings H05K3/0091 takes precedence; methods for intermediate insulating layers for build-up multilayer circuits H05K3/4673
• CPC Class Codes: H05K 3/284 : for encapsulating mounted components H05K1/185 takes precedence

Abstract

A semiconductor package and a method and a substrate for making the package are disclosed. The substrate of an exemplary package includes metal circuit patterns covered by a layer of an insulative nonphotoimageable solder mask material. A plurality of apertures are formed by laser ablation through the nonphotoimageable solder mask layer so as to expose a selected region of at least some of the circuit patterns. A bond wire is electrically connected between a semiconductor chip connected to the substrate and the respective circuit patterns through the laser-formed aperture over the circuit pattern.

Claims

1. A semiconductor package comprising:

a substrate including a first circuit pattern;

a layer of an insulative solder mask material over the substrate and the first circuit pattern, wherein the layer of solder mask material includes at least one laser-formed aperture; and

a semiconductor chip electrically connected to the first portion of the circuit pattern through the laser-formed aperture.

2. The semiconductor package of claim 1, wherein the solder mask layer is a nonphotoimageable material.

3. The semiconductor package of claim 2, further comprising a chip pad on the substrate, said chip pad having a first surface exposed through a laser-formed aperture in the nonphotoimageable solder mask layer, wherein the semiconductor chip is connected to the first surface through the laser formed aperture.

4. The semiconductor package of claim 1, wherein the insulative solder mask layer is an epoxy material devoid of acrylates and photoinitiator compounds.

5. A semiconductor package comprising:

a substrate including an electrically conductive circuit pattern;

a layer of an insulative nonphotoimageable solder mask material over the substrate and covering at least a portion of the circuit pattern, wherein at least a first portion of the circuit pattern is superimposed by a laser-formed aperture; and

a semiconductor chip electrically connected to the circuit pattern.

6. The semiconductor package of claim 5, further comprising a chip pad on the substrate, said chip pad having a first surface exposed through a laser-formed aperture in the nonphotoimageable solder mask layer, wherein the semiconductor chip is connected to the first surface through the laser formed aperture.

7. The semiconductor package of claim 5, wherein the semiconductor chip is electrically connected to the circuit pattern through the laser-formed aperture.

8. The semiconductor package of claim 5, wherein the first portion of the circuit pattern superimposed by the laser-formed aperture is an input/output terminal of the semiconductor package.

9. The semiconductor package of claim 5, further comprising a solder ball fused to the first portion of the circuit pattern through the laser-formed aperture.

10. The semiconductor package of claim 5, wherein the semiconductor chip is electrically connected to the first portion of the circuit pattern through the laser-formed aperture.

11. A method of making a semiconductor package, the method comprising:

providing a substrate including a first circuit pattern and a layer of an insulative solder mask material over the substrate and the circuit pattern, wherein the layer of solder mask material includes at least one laser-formed aperture; and

electrically connecting a semiconductor chip to a first portion of the first circuit pattern through the laser-formed aperture.

12. The method of claim 11, further comprising covering the semiconductor chip, the first portion of the circuit pattern, and at least a portion of the substrate and solder mask with a plastic encapsulant.

13. The method of claim 12, wherein said covering step is performed by molding.

14. The method of claim 12, wherein the solder mask layer is a nonphotoimageable material.

15. The method of claim 11, wherein the solder mask layer is a nonphotoimageable material.

16. The method of claim 11, wherein the insulative solder mask layer is an epoxy based material devoid of acrylates and photoinitiator compounds.

17. A semiconductor package made using the method of claim 11.

18. A semiconductor package made using the method of claim 14.

19. A semiconductor package made using the method of claim 15.

23. The method of claim 11, wherein electrically connecting the semiconductor chip to the first portion of the first circuit pattern comprises coupling a metal conductor between the semiconductor chip and the first portion of the first circuit pattern, said metal conductor extending through the laser-formed aperture.

20. A method of making an electrically interconnective substrate, the method comprising:

providing an insulative sheet including a plurality of conductive first circuit patterns on a first surface thereof;

applying a layer of an insulative nonphotoimageable solder mask material over the first circuit patterns; and

forming

forming a plurality of apertures through the nonphotoimageable solder mask layer using a laser so as to expose a selected region of at least some of the first circuit patterns.

21. A circuit board comprising:

an insulative core layer with a metal first circuit pattern on an exterior surface thereof; and

a layer of an insulative nonphotoimageable solder mask material overlying the first circuit pattern, wherein the layer of solder mask material includes at least one laser-formed aperture exposing a portion of the first circuit pattern.

22. The circuit board of claim 21, further comprising a metal conductor electrically coupled to the exposed portion of the first circuit pattern through the laser-formed aperture.

24. A method of making an electrical assembly, the method comprising:

providing a substrate including a first circuit pattern and a layer of an insulative material over the substrate and the circuit pattern, wherein the layer of the insulative material includes at least one laser-formed aperture exposing a portion of the circuit pattern; and

electrically connecting a metal conductor to the exposed portion of the first circuit pattern through the laser-formed aperture.

25. The method of claim 24, further comprising coupling a semiconductor chip to the substrate, and electrically connecting the metal conductor to the semiconductor chip.

26. The method of claim 24, further comprising applying the layer of the insulative material in a liquid state over the substrate, solidifying the layer of insulative material, and using a laser to form the laser-formed aperture in the solidified layer of the insulative material.

27. The method of claim 24, further comprising covering the insulative layer, the metal connector, and the laser formed aperture with a plastic encapsulant.