Pre-treatment of low-k dielectric for prevention of photoresist poisoning

• US 6,534,397 B1
• Filed: 07/13/2001
• Issued: 03/18/2003
• Est. Priority Date: 07/13/2001
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Wang, Fei, Okada, Lynne A., Gabriel, Calvin T.
• Primary Examiner(s): Whitehead, Jr., Carl
• Assistant Examiner(s): MENZ, LAURA MARY
• Application Number:
  US09/903,758
• Time in Patent Office: 613 Days
• Field of Search: 438/597, 438/605, 438/622, 438/687, 438/707, 438/618, 438/623, 438/629, 438/633, 438/738, 430/314, 430/330, 430/329, 430/118, 156/345, 156/630
• US Class Current: 438/633
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76826 by contacting the layer with gases, liquids or plasmas

Abstract

Deleterious poisoning of patterned photoresist masking layers accompanying plasma ashing/etching of photoresist and/or low-k dielectric layers is eliminated, or at least substantially reduced, by pretreating exposed surfaces of the low-k dielectric layer(s) with hydrogen, e.g., by contact with a hydrogen plasma prior to plasma ashing/etching. The invention enjoys particular utility in the formation of dual damascene openings in dielectric layers as part of metallization processing of semiconductor IC devices.

Claims

1. A method of eliminating, or at least substantially reducing, photoresist poisoning during recess patterning of a layer of a material, comprising the sequential steps of:

(a) forming a first photoresist layer on an upper surface of said layer;

(b) patterning said first photoresist layer to include at least one opening therein having a first width;

(c) forming at least one first recess in said upper surface of said layer utilizing said patterned first photoresist layer as a mask, said at least one first recess having a first width substantially corresponding to said first width of said at least one opening in said first photoresist layer and extending for a first depth below said surface of said layer;

(d) treating exposed surfaces of said layer to eliminate, or at least substantially reduce the amount of, at least one contaminant or constituent thereof which can poison a second photoresist layer subsequently formed in contact with said upper surface of said layer;

(e) removing said first photoresist layer; and

(f) forming a second photoresist layer on said upper surface of said layer;

wherein poisoning of said second photoresist layer by entry thereinto of said at least one contaminant or constituent of said layer is eliminated or at least substantially reduced due to said surface treating of step (d).

2. The method as in claim 1, further comprising the steps of:

(g) patterning said second photoresist layer to form at least one opening therein, said at least one opening in said second photoresist layer being vertically aligned with said at least one first recess in said layer and having a second width greater than said first width; and

(h) forming at least one second recess in an upper portion of said layer utilizing said second patterned photoresist layer as a mask, said at least one second recess having a second width substantially corresponding to said second, greater width of said at least one opening in said second photoresist layer, said at least one second recess communicating with said at least one first recess and extending for a second depth below said surface of said layer, said second depth being less than said first depth.

3. The method as in claim 1, wherein:

step (a) comprises forming said first photoresist layer on the surface of a layer comprised of at least one low-k dielectric material having a dielectric constant less than about 3.9.

4. The method as in claim 3, wherein:

step (a) comprises forming said photoresist layer on the surface of a layer comprised of a laminate of layers of at least one low-k dielectric material.

5. The method as in claim 4, wherein:

step (a) comprises forming said first photoresist layer on the surface of a laminate of layers each comprised of a low-k dielectric material selected from the group consisting of hydrogen silsesquioxane-based ceramic polymers, poly(arylene) ether-based organic polymers, benzocyclobutene-based materials, aromatic hydrocarbon-based polymers, carbon-doped silicon oxide, hybrid siloxane-organic polymers, nanoporous silica, halogen-doped silicon dioxides obtained from tetraethyl orthosilicate, and fluorine-doped silica glasses.

6. The method as in claim 1, wherein:

step (c) comprises forming said at least one recess in said upper surface of said layer by an anisotropic etching process.

7. The method as in claim 6, wherein:

step (c) comprises anisotropic etching utilizing a reactive plasma.

8. The method as in claim 1, wherein:

step (d) comprises treating said exposed surfaces of said layer with hydrogen.

9. The method as in claim 8, wherein:

step (d) comprises performing said treating by contacting said exposed surfaces with hydrogen.

10. The method as in claim 9, wherein:

step (d) comprises contacting said exposed surfaces with a hydrogen plasma.

11. The method as in claim 1, wherein:

step (e) comprises removing said first photoresist layer by plasma ashing.

12. The method as in claim 11, wherein:

step (e) comprises plasma ashing said first photoresist layer in a nitrogen-containing atmosphere.

13. The method as in claim 2, wherein:

step (h) comprises forming said at least one second recess in said upper portion of said layer by an anisotropic etching process utilizing said patterned second photoresist layer as a mask, said etching terminating at an etch stop layer within said layer at said second depth below said surface.

14. The method as in claim 13, wherein:

step (h) comprises anisotropic etching utilizing a reactive plasma.

15. The method according to claim 1, wherein the at least one contaminant or constituent comprises nitrogen atoms or molecules.

16. A method of manufacturing a semiconductor device, comprising the sequential steps of:

(a) providing a workpiece comprising;

(i) a semiconductor substrate including at least one active device region or component formed therein or thereon;

(ii) a dielectric layer overlying said semiconductor substrate and including at least one metal feature in-laid in an upper surface of said dielectric layer;

(iii) a thin capping layer formed over at least the upper surface of said at least one metal feature; and

(iv) an interlayer dielectric layer formed over said thin capping layer;

(b) forming a first photoresist layer on an upper surface of said interlayer dielectric layer;

(c) patterning said first photoresist layer to include at least one opening therein having a first width;

(d) forming at least one first recess in said upper surface of said interlayer dielectric layer utilizing said patterned first photoresist layer as a mask, said at least one first recess having a first width substantially corresponding to said first width of said at least one opening in said first photoresist layer and extending through said interlayer dielectric layer to said thin capping layer;

(e) treating exposed surfaces of said interlayer dielectric layer to eliminate, or at least substantially reduce the amount of, at least one contaminant or constituent thereof which can poison a second photoresist layer subsequently formed on said upper surface of said interlayer dielectric layer;

(f) removing said first photoresist layer;

(g) forming a second photoresist layer on said upper surface of said interlayer dielectric layer;

(h) patterning said second photoresist layer to form at least one opening therein, said at least one opening in said second photoresist layer being vertically aligned with said at least one first recess and having a second width greater than said first width; and

(i) forming at least one second recess extending partway through said interlayer dielectric layer utilizing said patterned second photoresist layer as a mask, said at least one second recess having a second width substantially corresponding to said second, greater width of said at least one opening in said second photoresist layer and communicating with said at least one first recess.

17. The method as in claim 16, wherein:

step (a) comprises providing a workpiece wherein said interlayer dielectric layer (iv) further includes;

(iv₁) a first, lower interlayer dielectric layer formed over said thin capping layer;

(iv₂) a thin etch stop layer formed over said first interlayer dielectric layer; and

(iv₃) a second, upper interlayer dielectric layer formed over said thin etch stop layer.

18. The method as in claim 17, wherein:

step (a) comprises providing a workpiece wherein each of said first, lower and second, upper interlayer dielectric layers comprises a low-k dielectric material having a dielectric constant less than about 3.9, selected from the group consisting of hydrogen silsesquioxane-based ceramic polymers, poly(arylene) ether-based organic polymers, benzocyclobutene-based materials, aromatic hydrocarbon-based polymers, carbon-doped silicon oxide, hybrid siloxane-organic polymers, nanoporous silica, halogen-doped silicon dioxides obtained from tetraethyl orthosilicate, and fluorine-doped silica glasses;

step (e) comprises treating exposed surfaces of said first and second interlayer dielectric layers to eliminate, or at least substantially reduce the amount of nitrogen atoms and/or molecules thereon or thereat by contacting said exposed surfaces with a hydrogen plasma; and

step (f) comprises removing said first photoresist layer by plasma ashing in a nitrogen-containing atmosphere.

19. The method as in claim 18, wherein:

step (d) comprises anisotropic etching utilizing a reactive plasma; and

step (i) comprises anisotropic etching utilizing a reactive plasma and terminating etching of said at least one second recess at said thin etch stop layer.

20. The method as in claim 16, further comprising the steps of:

(j) removing said second photoresist layer;

(k) removing said thin capping layer overlying said upper surface of said at least one in-laid metal feature at the bottom of said at least one first recess; and

(l) filling said at least one first and said at least one second communicating recesses with a metal plug to form at least one electrically conductive via in contact with said at least one in-laid metal feature and at least one electrically conductive line in contact with said at least one electrically conductive via.

21. The method as in claim 16, wherein:

step (a) comprises providing a workpiece wherein said semiconductor substrate comprises silicon (Si), said at least one in-laid metal feature comprises copper (Cu) or a Cu-based alloy, and said thin capping layer comprises a silicon nitride or oxynitride.