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Reduced terminal testing system

  • US 6,534,785 B1
  • Filed: 08/14/2000
  • Issued: 03/18/2003
  • Est. Priority Date: 09/13/1996
  • Status: Expired due to Term
First Claim
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1. A semiconductor wafer comprising:

  • a substrate;

    a plurality of dice located on the substrate, the plurality of dice including circuitry for placing an individual die of the plurality of dice into a mode, said mode including one of a predetermined testing mode for testing a plurality of dice, a functional test mode, and a parametric test mode, upon receipt of an alternating signal having a predetermined characteristic by the circuitry, the alternating signal including one of at least one test pattern signal and information in a signal form; and

    a conductive path connected to the circuitry providing the alternating signal to the circuitry.

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