Power MOS device with improved gate charge performance

• US 6,534,825 B2
• Filed: 08/14/2002
• Issued: 03/18/2003
• Est. Priority Date: 12/20/1999
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Calafut, Daniel S.
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): Rao, Shrinivas H.
• Application Number:
  US10/219,603
• Publication Number:
  US 20020190282A1
• Time in Patent Office: 216 Days
• Field of Search: 257/335, 257/337, 257/338, 257/340, 257/341, 438/270, 438/271, 438/587, 438/593
• US Class Current: 257/335
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4916 the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A double-diffused metal-oxide-semiconductor (“DMOS”) field-effect transistor with an improved gate structure. The gate structure includes a first portion of a first conductivity type for creating electron flow from the source to the drain when a charge is applied to the gate. The gate structure includes a second portion of a second conductivity type having a polarity that is opposite a polarity of the first conductivity type, for decreasing a capacitance charge under the gate. A second structure for decreasing a capacitance under the gate includes an implant region in the semiconductor substrate between a channel region, where the implant region is doped to have a conductivity opposite the channel region.

Claims

1. A double-diffused metal oxide semiconductor (DMOS) device comprising;

a body region of a first conductivity type in a semiconductor substrate having a drain region of a second conductivity type;

a source region of the second conductivity type in the body region

a trench formed in the semiconductor substrate;

a dielectric layer lining the trench;

a first polysilicon gate portion formed to an intermediate depth of the trench;

a dopant of the first conductivity type implanted into the first polysilicon gate portion;

a second polysilicon gate portion in the trench formed over the first polysilicon gate portion to a level substantially equal to a top surface of the silicon substrate, wherein the second polysilicon gate portion is formed by etching an intermediate portion of said second polysilicon gate portion down to the first polysilicon gate portion to form Opposite side walls;

a dopant of the second conductivity type implanted into the second polysilicon gate portion; and

a polycide strap layer formed over the first polysilicon gate portion, in the intermediate portion, and on the opposite side walls of the second polysilicon gate portion.

2. The DMOS device of claim 1 further comprising a conductive material on the polycide strap layer and being at a level substantially equal to the top surface of the silicon substrate.

3. The DMOS device of claim 1 wherein the first conductivity type is p-type and the second conductivity type is u-type.

4. The DMOS device of claim 1, further comprising,

an insulator over the polycide strap layer, in the trench and Over the top of the trench.

5. The DMOS device of claim 4 wherein the insulator extends over the source region.

6. The DMOS device of claim 4 further comprising:

a metal layer formed over the insulator.

7. The DMOS device of claim 1 wherein the source region is formed after the trench is formed.

8. The DMOS device of claim 1 further comprising an insulator over the polycide strap layer, in the trench and Over the lop of the trench, and wherein the insulator comprises borophosphosilicon glass (BPSG).

9. The DMOS device of claim 1 wherein the first polysilicon gate portion further includes the dopant of the first conductivity type implanted therein in an amount sufficient to minimize the capacitance in an accumulation area for a predetermined voltage.

10. The DMOS device of claim 1 further comprising an insulator over the polycide strap layer, in the trench and over the top of the trench, and a metal layer over the insulator to provide electrical contact to die source region.

11. The DMOS device of claim 1 wherein the DMOS device is a power MOS device.