Integrated circuit device including a deep well region and associated methods

• US 6,534,828 B1
• Filed: 09/19/2000
• Issued: 03/18/2003
• Est. Priority Date: 09/19/2000
• Status: Expired due to Term

• Current Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Kocon, Christopher Boguslaw
• Primary Examiner(s): Flynn, Nathan J.
• Assistant Examiner(s): Dickey, Thomas L
• Application Number:
  US09/664,024
• Time in Patent Office: 910 Days
• Field of Search: 257/327, 257/341, 257/328, 257/329-332, 257/334
• US Class Current: 257/341
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

An integrated circuit device includes a semiconductor layer of a first conductivity type, a plurality of spaced apart semiconductor pillars extending outwardly from said semiconductor layer and defining trenches therebetween, a respective gate structure in each trench, and at least one deep well region having the second conductivity type and being positioned to extend in the semiconductor layer between an adjacent pair of corresponding semiconductor pillars and beneath a bottom of at least one trench defining therein at least one inactive gate structure. The at least one deep well region may be positioned so that at least one trench does not include a deep well region therebeneath to define at least one active gate structure. Each semiconductor pillar may be of a second conductivity type opposite the first conductivity type.

Claims

1. An integrated circuit device comprising:

a semiconductor layer of a first conductivity type;

a plurality of spaced apart semiconductor pillars extending outwardly from said semiconductor layer and defining trenches therebetween, each semiconductor pillar being of a second conductivity type opposite the first conductivity type;

a respective gate structure in each trench; and

at least one deep well region having the second conductivity type and being positioned to extend in said semiconductor layer between an adjacent pair of corresponding semiconductor pillars and beneath a bottom of at least one trench defining therein at least one inactive gate structure, said at least one deep well region being positioned so that at least one trench does not include a deep well region therebeneath to define at least one active gate structure.

2. The device of claim 1 wherein said at least deep well region comprises a plurality of deep well regions arranged to define alternating active and inactive gate structures.

3. The device of claim 1 wherein said at least one deep well region has a dopant concentration in a range of about 1×

10¹⁶ to 1×

10¹⁸ cm<sup>−

3</sup>.

4. The device of claim 1 wherein each semiconductor pillar comprises an upper portion having the first conductivity type.

5. The device of claim 4 wherein said at least one inactive gate structure is connected to the upper portion of each semiconductor pillar.

6. The device of claim 1 wherein said at least one inactive gate structure and said at least one active gate structure are connected together.

7. The device of claim 1 wherein each gate structure comprises a gate oxide layer adjacent said trench and a conducting layer adjacent said gate oxide layer.

8. The device of claim 7 wherein said conducting layer comprises polysilicon.

9. The device of claim 1 further comprising a semiconductor substrate adjacent said semiconductor layer on a side thereof opposite said semiconductor pillars.

10. The device of claim 9 wherein said semiconductor substrate comprises silicon.

11. The device of claim 9 wherein said semiconductor substrate is more heavily doped than said semiconductor layer.

12. The device of claim 9 wherein said semiconductor substrate is of the first conductivity type thereby defining a metal oxide semiconductor field effect transistor.

13. The device of claim 9 wherein said semiconductor substrate is of the second conductivity type thereby defining a insulated gate bipolar transistor.

14. The device of claim 1 wherein the first conductivity type is N-type and the second conductivity type is P-type.

15. A MOS-gated integrated circuit device comprising:

a semiconductor substrate;

a semiconductor layer of a first conductivity type on said semiconductor substrate;

a plurality of spaced apart semiconductor pillars extending outwardly from said semiconductor layer and defining trenches therebetween, each semiconductor pillar being of a second conductivity type opposite the first conductivity type;

a respective MOS gate structure in each trench comprising a gate oxide layer adjacent said trench and a conducting layer adjacent said gate oxide layer;

a plurality of deep well regions having the second conductivity type, each deep well region being positioned to extend in said semiconductor layer between an adjacent pair of semiconductor pillars and beneath a bottom of a corresponding trench defining therein an inactive gate structure, said deep well regions being spaced apart to define active gate structures therebetween.

16. The device of claim 15 wherein each deep well region has a dopant concentration of about 1×

10¹⁶ to 1×

10¹⁸ cm<sup>−

3</sup>.

17. The device of claim 15 wherein said plurality of deep well regions are spaced apart to define alternating active and inactive gate structures.

18. The device of claim 15 wherein each semiconductor pillar comprises an upper portion having the first conductivity type.

19. The device of claim 18 wherein said at least one inactive gate structure is connected to the upper portion of each semiconductor pillar.

20. The device of claim 15 wherein said inactive gate structure and said active gate structure are connected together.

21. The device of claim 15 wherein said conducting layer comprises polysilicon.

22. The device of claim 15 wherein said semiconductor substrate comprises silicon.

23. The device of claim 15 wherein said semiconductor substrate is of the first conductivity type thereby defining a metal oxide semiconductor field effect transistor.

24. The device of claim 15 wherein said semiconductor substrate is of the second conductivity type thereby defining an insulated gate bipolar transistor.

25. The device of claim 15 wherein said semiconductor substrate is more heavily doped than said semiconductor layer.

26. The device of claim 15 wherein the first conductivity type is N-type and the second conductivity type is P-type.