MOSFET semiconductor device

• US 6,534,836 B1
• Filed: 10/10/2000
• Issued: 03/18/2003
• Est. Priority Date: 10/25/1999
• Status: Expired due to Term

• Current Assignee: Ablic Inc. (Minebea Mitsumi, Inc.)
• Original Assignee: Seiko Instruments Incorporated (Seiko Group)
• Inventors: Osanai, Jun
• Primary Examiner(s): Flynn, Nathan J.
• Assistant Examiner(s): Wilson, Scott R
• Application Number:
  US09/685,503
• Time in Patent Office: 889 Days
• Field of Search: H01/L 2.978, H01/L 2.122, H01/L 2.9225, 257/401, 257/341, 257/493, 257/335, 257/139, 438/284
• US Class Current: 257/401
• CPC Class Codes: H01L 21/2255 the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
• CPC Class Codes: H01L 21/2257 the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors

Abstract

A power MOSFET semiconductor device high in breakdown voltage and low in resistance can be manufactured at a low cost and in a short turnaround time. In a planar-type power MOSFET, a manufacture method comprises forming a trench in a drift region, and forming a body diffusion layer on a trench side wall and bottom portion (forming the trench and subsequently performing diffusion) to obtain a structure. Deep body diffusion formation is effective for obtaining the high breakdown voltage and low resistance, but to attain the structure, usually epitaxial growth and selective formation of a deep body region have to be performed a plurality of times, and with an increase of manufacture steps, souring of manufacture cost and lengthening of manufacture period are caused. However, the present structure can further simply bring about the similar effect. It is possible to supply the power MOSFET semiconductor device at the low cost and in the short manufacture turnaround time.

Claims

1. A semiconductor device comprising:

a high impurity concentration first conductivity type semiconductor substrate;

a low impurity concentration first conductivity type semiconductor layer formed on a surface of the semiconductor substrate;

a trench selectively formed in a surface of the low impurity concentration first conductivity type semiconductor layer;

first conductivity type polycrystalline silicon filled inside the trench;

a low impurity concentration second conductivity type semiconductor diffusion layer formed on a side wall and a bottom wall of the trench;

a relatively shallow low impurity concentration second conductivity type semiconductor diffusion layer partially overlapped with the low impurity concentration second conductivity type semiconductor diffusion layer and selectively formed on the surface of the low impurity concentration first conductivity type semiconductor layer;

a high impurity concentration first conductivity type semiconductor diffusion layer selectively formed on the relatively shallow low impurity concentration second conductivity type semiconductor diffusion layer;

a gate insulation film formed on the low impurity concentration first conductivity type semiconductor layer and the relatively shallow low impurity concentration second conductivity type semiconductor diffusion layer; and

a gate electrode selectively formed on the gate insulation film.

2. A semiconductor device according to claim 1;

further comprising an insulation film filled inside the trench formed in the low impurity concentration first conductivity type semiconductor layer.

3. A semiconductor device according to claim 1;

wherein the low impurity concentration first conductivity type semiconductor layer comprises an epitaxially grown layer.

4. A semiconductor device according to claim 1;

wherein a depth of the trench is in the range of about 3 to 10 μ

m.

5. A semiconductor device according to claim 1;

wherein the low impurity concentration second conductivity type semiconductor diffusion layer has an impurity density in the range of about 1×

10¹⁶/cm³ to 1×

10¹⁸/cm³, and a diffusion depth thereof is in the range of about 0.5 to 2 μ

m.

6. A semiconductor device comprising:

a high impurity concentration first conductivity type semiconductor substrate comprised of single crystal silicon including antimony or arsenic with a density of 1×

10¹⁹/cm³ to 1×

10²⁰/cm³;

a low impurity concentration first conductivity type semiconductor layer formed on a surface of the semiconductor substrate;

a trench selectively formed in a surface of the low impurity concentration first conductivity type semiconductor layer;

a low impurity concentration second conductivity type semiconductor diffusion layer formed on a side wall and a bottom wall of the trench;

a relatively shallow low impurity concentration second conductivity type semiconductor diffusion layer partially overlapped with the low impurity concentration second conductivity type semiconductor diffusion layer and selectively formed on the surface of the low impurity concentration first conductivity type semiconductor layer;

a high impurity concentration first conductivity type semiconductor diffusion layer selectively formed on the relatively shallow low impurity concentration second conductivity type semiconductor diffusion layer;

a gate insulation film formed on the low impurity concentration first conductivity type semiconductor layer and the relatively shallow low impurity concentration second conductivity type semiconductor diffusion layer; and

a gate electrode selectively formed on the gate insulation film.

7. A semiconductor device comprising:

a high impurity concentration first conductivity type semiconductor substrate;

a low impurity concentration first conductivity type semiconductor layer formed on a surface of the semiconductor substrate, the low impurity concentration first conductivity type semiconductor layer comprising an epitaxially grown layer having a phosphorous density of 1×

10¹⁴/cm³ to 1×

10¹⁶/cm³;

a trench selectively formed in a surface of the low impurity concentration first conductivity type semiconductor layer;

a low impurity concentration second conductivity type semiconductor diffusion layer formed on a side wall and a bottom wall of the trench;

a relatively shallow low impurity concentration second conductivity type semiconductor diffusion layer partially overlapped with the low impurity concentration second conductivity type semiconductor diffusion layer and selectively formed on the surface of the low impurity concentration first conductivity type semiconductor layer;

a high impurity concentration first conductivity type semiconductor diffusion layer selectively formed on the relatively shallow low impurity concentration second conductivity type semiconductor diffusion layer;

a gate insulation film formed on the low impurity concentration first conductivity type semiconductor layer and the relatively shallow low impurity concentration second conductivity type semiconductor diffusion layer; and

a gate electrode selectively formed on the gate insulation film.

8. A semiconductor device comprising:

a high impurity concentration first conductivity type semiconductor substrate;

a low impurity concentration first conductivity type semiconductor layer formed on a surface of the semiconductor substrate, the low impurity concentration first conductivity type semiconductor layer comprising an epitaxially grown layer having a thickness in the range of about five to a dozen μ

m;

a trench selectively formed in a surface of the low impurity concentration first conductivity type semiconductor layer;

a low impurity concentration second conductivity type semiconductor diffusion layer formed on a side wall and a bottom wall of the trench;

a relatively shallow low impurity concentration second conductivity type semiconductor diffusion layer partially overlapped with the low impurity concentration second conductivity type semiconductor diffusion layer and selectively formed on the surface of the low impurity concentration first conductivity type semiconductor layer;

a high impurity concentration first conductivity type semiconductor diffusion layer selectively formed on the relatively shallow low impurity concentration second conductivity type semiconductor diffusion layer;

a gate insulation film formed on the low impurity concentration first conductivity type semiconductor layer and the relatively shallow low impurity concentration second conductivity type semiconductor diffusion layer; and

a gate electrode selectively formed on the gate insulation film.

9. A semiconductor device comprising:

a high impurity concentration first conductivity type semiconductor substrate;

a low impurity concentration first conductivity type semiconductor layer epitaxially grown on a surface of the semiconductor substrate;

a trench selectively formed in a surface of the low impurity concentration first conductivity type semiconductor layer, the trench being slightly shallower than the epitaxially grown layer a low impurity concentration second conductivity type semiconductor diffusion layer formed on a side wall and a bottom wall of the trench;

a relatively shallow low impurity concentration second conductivity type semiconductor diffusion layer partially overlapped with the low impurity concentration second conductivity type semiconductor diffusion layer and selectively formed on the surface of the low impurity concentration first conductivity type semiconductor layer;

a high impurity concentration first conductivity type semiconductor diffusion layer selectively formed on the relatively shallow low impurity concentration second conductivity type semiconductor diffusion layer;

a gate insulation film formed on the low impurity concentration first conductivity type semiconductor layer and the relatively shallow low impurity concentration second conductivity type semiconductor diffusion layer; and

a gate electrode selectively formed on the gate insulation film.

10. A semiconductor device comprising:

a semiconductor substrate;

a semiconductor layer having a first conductivity type formed on the semiconductor substrate;

a trench formed in the semiconductor layer, the inside of the trench being filled with polycrystalline silicon;

a first semiconductor diffusion layer having a second conductivity type formed on a side wall and a bottom wall of the trench;

a second semiconductor diffusion layer having the second conductivity type formed on the surface of the first conductivity type semiconductor layer partially overlapping the first semiconductor diffusion layer;

a third semiconductor diffusion layer having the first conductivity type formed on the second semiconductor diffusion layer;

a gate insulation film formed on the first conductivity type semiconductor layer and the second conductivity type semiconductor diffusion layer; and

a gate electrode formed on the gate insulation film.

11. A semiconductor device according to claim 10;

wherein the semiconductor layer formed on the semiconductor substrate is an epitaxially grown film.

12. A semiconductor device comprising:

a semiconductor substrate comprised of single crystal silicon including antimony or arsenic with a density of 1×

10¹⁹/cm³ to 1×

10²⁰/cm³;

a semiconductor layer having a first conductivity type formed on the semiconductor substrate;

a trench formed in the semiconductor layer;

a first semiconductor diffusion layer having a second conductivity type formed on a side wall and a bottom wall of the trench;

a second semiconductor diffusion layer having the second conductivity type formed on the surface of the first conductivity type semiconductor layer partially overlapping the first semiconductor diffusion layer;

a third semiconductor diffusion layer having the first conductivity type formed on the second semiconductor diffusion layer;

a gate insulation film formed on the first conductivity type semiconductor layer and the second conductivity type semiconductor diffusion layer; and

a gate electrode formed on the gate insulation film.

13. A semiconductor device comprising:

a high impurity concentration first conductivity type semiconductor substrate, the first conductivity type semiconductor layer comprising an epitaxially grown layer having a phosphorous density of 1×

10¹⁴/cm³ to 1×

10¹⁶/cm³;

a low impurity concentration first conductivity type semiconductor layer formed on a surface of the semiconductor substrate;

a trench selectively formed in a surface of the low impurity concentration first conductivity type semiconductor layer;

a low impurity concentration second conductivity type semiconductor diffusion layer formed on a side wall and a bottom wall of the trench;

a relatively shallow low impurity concentration second conductivity type semiconductor diffusion layer partially overlapped with the low impurity concentration second conductivity type semiconductor diffusion layer and selectively formed on the surface of the low impurity concentration first conductivity type semiconductor layer;

a high impurity concentration first conductivity type semiconductor diffusion layer selectively formed on the relatively shallow low impurity concentration second conductivity type semiconductor diffusion layer;

a gate insulation film formed on the low impurity concentration first conductivity type semiconductor layer and the relatively shallow low impurity concentration second conductivity type semiconductor diffusion layer; and

a gate electrode selectively formed on the gate insulation film.

14. A semiconductor device according to claim 13;

wherein a thickness of the epitaxially grown layer is in the range of about five to a dozen μ

m.

15. A semiconductor device according to claim 13;

wherein the trench is slightly shallower than the epitaxially grown layer.

16. A semiconductor device according to claim 15;

wherein a depth of the trench is in the range of about 3 to 10 μ

m.

17. A semiconductor device according to claim 15;

wherein the first semiconductor diffusion layer has an impurity density in the range of about 1×

10¹⁶/cm³ to 1×

10¹⁸/cm³, and a diffusion depth thereof is in the range of about 0.5 to 2 μ

m.