Continuous antifuse material in memory structure

• US 6,534,841 B1
• Filed: 12/14/2001
• Issued: 03/18/2003
• Est. Priority Date: 12/14/2001
• Status: Expired due to Fees

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Company (HP Inc.)
• Inventors: Eldredge, Kenneth J., Van Brocklin, Andrew L., Fricke, Peter, Wang, S. Jonathan, Perner, Frederick A
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): SMITH, BRADLEY
• Application Number:
  US10/017,567
• Time in Patent Office: 459 Days
• Field of Search: 257/50, 257/530, 438/129, 438/130
• US Class Current: 257/530
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 20/25 One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links

Abstract

A memory structure has an antifuse material that is unpatterned and sandwiched between each of a plurality of antifuse electrode pairs. The antifuse material is continuous between the antifuse electrode pairs. Furthermore the present invention includes a memory structure comprising a plurality of antifuse electrode pairs forming a plurality of row conductors and a plurality of middle conductors in electrical communication with a plurality of control elements.

Claims

1. A memory structure, comprising:

a plurality of control elements;

a plurality of antifuse electrode pairs forming a plurality of row conductors and a plurality of middle conductors in electrical communication with the plurality of control elements and

an antifuse material continuously unpatterned and sandwiched between each of the plurality of antifuse electrode pairs wherein the antifuse material has a non-planar top surface and is conformally situated with good step coverage over each of the row conductors in said plurality of row conductors.

2. A memory structure, comprising:

a plurality of control elements;

a plurality of antifuse structures each having an antifuse electrode pair containing at least one first conductor and at least one second conductor, the antifuse electrode pair electrically-insulated by a common and continuous antifuse layer wherein each the antifuse structures has a non-planar top surface and is conformally situated with good step coverage over each first conductor contacting the respective antifuse structure, and wherein each second conductor is in electrical communication with one of the plurality of control elements.

3. The memory structure as defined in claim 2, further comprising:

a dielectric layer disposed over the common and continuous antifuse layer and contacting one antifuse electrode in each said pair;

at least one third conductor disposed over the dielectric layer; and

the at least one first conductor functioning as the other antifuse electrode in each said pair.

4. A memory structure, comprising:

a plurality of stacked layers each being separated from adjacent stacked layers by an interlayer dielectric, wherein each stacked layer include a pair of antifuse electrodes and a plurality of tunnel junction control elements in electrical communication with one of the pair of antifuse electrodes; and

an antifuse material extending continuously between the pairs of antifuse electrodes of each of the stacked layers.

5. A memory structure on a substrate, comprising:

a plurality of stacked layers each including;

an interlayer dielectric that extends continuously across the substrate;

an antifuse material that further extends continuously across the substrate over the interlayer dielectric;

a plurality of antifuse electrodes each having one said antifuse electrode separated from the other pair by the antifuse material; and

a plurality of tunnel junction control elements in electrical communication with one of the pair of antifuse electrodes.

6. The memory structure as defined in claim 5, wherein the interlayer dielectric of each said plurality of stacked layers separates one stacked layer from an adjacent stacked layer.

7. A memory structure comprising a plurality of word lines disposed next to a continuous antifuse layer which is disposed next to a column line in electrical communication with a plurality of tunnel junction control elements, wherein each tunnel junction control element is physically separated from a respective word line by the continuous antifuse layer.

8. A memory structure, comprising:

a plurality of row conductors;

a continuous blanket of antifuse material disposed upon the plurality of row conductors;

at least one tunnel junction control element substantially aligned over each said row conductor and separated therefrom by the antifuse material; and

a column conductor aligned over each at least one tunnel junction control element.

9. The memory structure as defined in claim 8, wherein:

each said row conductor, each said tunnel junction control element, and each said column conductor is included in an individual memory cell;

each said individual memory cell is vertically stacked with another said memory cell; and

each said individual memory cell shares one of the row and column conductors thereof with another said memory cell that is vertically adjacent thereto.

10. A memory structure, comprising:

a plurality of row conductors;

a continuous blanket of antifuse material disposed upon the plurality of row conductors;

at least one control element substantially aligned over each said row conductor and separated therefrom by the antifuse material; and

a column conductor aligned over each at least one control element;

wherein the antifuse material has a non-planar top surface and is conformally situated with good step coverage over and between each of the row conductors in said plurality of row conductors.

11. A memory structure, comprising:

a plurality of row conductors;

a continuous blanket of antifuse material disposed upon the plurality of row conductors;

at least one control element substantially aligned over each said row conductor and separated therefrom by the antifuse material; and

a column conductor aligned over each at least one control element;

a first diffusion barrier upon the antifuse material that is upon each of the row conductors;

an interface metal between the first diffusion barrier and each at least one control element; and

a second diffusion barrier between each at least one control element and the respective column conductor.

12. A memory structure in an integrated circuit, comprising:

an interlayer dielectric;

an electrically conductive row conductor over the interlayer dielectric;

an unpatterned antifuse material over the row conductor, wherein the unpatterned antifuse material has a non-planar top surface and is conformally situated with good step coverage over the row conductor;

an electrically conductive column conductor; and

a plurality of control elements between the row and column conductors each being separated from the row conductor by the unpatterned antifuse material.

13. A memory structure, comprising:

a tunnel junction control element; and

an antifuse in electrical communication with the tunnel junction control element.

14. The memory structure as defined in claim 13, wherein:

the tunnel junction control element comprises an electrical insulator between a column conductor and an electrically resistive material; and

the antifuse comprises;

a row conductor;

an antifuse dielectric upon the row conductor; and

the electrically resistive material.

15. The memory structure as defined in claim 14, further comprising a plurality of vertically stacked pairs of said tunnel junction control element and said antifuse, wherein the row and column conductors in each said pair are shared with another said pair that is vertically adjacent thereto.

16. The memory structure as defined in claim 14, wherein the electrical insulator of the tunnel junction control element has:

an effective resistance not greater than that of the antifuse; and

a fusing voltage greater than or equal to that of the antifuse.

17. The memory structure as defined in claim 14, wherein each of the following is unpatterned:

the antifuse dielectric;

the electrically resistive material; and

the electrical insulator of the tunnel junction control element.

18. The memory structure as defined in claim 14, wherein:

the row conductor comprises aluminum;

the antifuse dielectric comprises alumina;

the electrically resistive material of the tunnel junction control element comprises doped silicon; and

the electrical insulator of the tunnel junction control element comprises