Semiconductor device, semiconductor element and method for producing same

• US 6,534,867 B1
• Filed: 09/26/2000
• Issued: 03/18/2003
• Est. Priority Date: 09/27/1999
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Arai, Norihisa, Shimizu, Kazuhiro, Shirota, Riichiro, Takeuchi, Yuji, Yaegashi, Toshitake, Kamiya, Eiji
• Primary Examiner(s): QUACH, TUAN N
• Application Number:
  US09/670,990
• Time in Patent Office: 903 Days
• Field of Search: 257/758, 257/763, 257/754, 257/755, 257/314, 257/315, 257/382, 257/383
• US Class Current: 257/754
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/41 of a memory region comprising a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/49 comprising different types of peripheral transistor
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A semiconductor device comprises: a semiconductor substrate; a plurality of first diffusion layers having a low impurity density, the first diffusion layers being formed on the surface of the semiconductor substrate; a plurality of second diffusion layers having a high impurity density, the second diffusion layers being formed on the surface of the semiconductor substrate; a plurality of first contacts, each of which contacts the first diffusion layers and each of which is formed of a semiconductor; and a plurality of second contacts, each of which contacts the second diffusion layers and each of which is formed of a metal.

Claims

1. A semiconductor device comprising:

a semiconductor substrate;

a plurality of first diffusion layers having a low impurity density, said first diffusion layers being formed on the surface of said semiconductor substrate;

a plurality of second diffusion layers having a high impurity density, said second diffusion layers being formed on the surface of said semiconductor substrate;

a plurality of first contacts, each of which contacts said first diffusion layers and each of which is formed of a semiconductor; and

a plurality of second contacts, each of which contacts said second diffusion layers and each of which is formed of a metal.

2. A semiconductor device as set forth in claim 1, which further comprises a memory cell array and a peripheral circuit and wherein said plurality of first diffusion layers are formed in said memory cell array and a part of said peripheral circuit, and said plurality of second diffusion layers are formed in other part of said peripheral circuit.

3. A semiconductor device as set forth in claim 1, wherein each of said plurality of first diffusion layers is a diffusion layer, to which a high voltage is applied, and which is connected to a corresponding one of said first contacts of said semiconductor, and

said each of said plurality of second diffusion layers is a diffusion layer, to which a high voltage is not applied, and which is connected to a corresponding one of said second contacts of said metal.

4. A semiconductor device as set forth in claim 1, which further comprises:

a high voltage circuit having a plurality of MOS transistors having a thick gate insulating film; and

a low voltage circuit having a plurality of MOS transistors having a thin gate insulating film,

wherein each of said plurality of first contacts is formed in said high voltage circuit portion, and

each of said plurality of second contacts is formed in said low voltage circuit portion.

5. A semiconductor device as set forth in claim 1, wherein at least the bottom portion of each of said first contacts is formed of semiconductor material, said bottom portion being connected to a corresponding one of said first diffusion layers, and the remaining portion of each of said first contacts is formed of a metal.

6. A semiconductor device as set forth in claim 1, wherein said semiconductor material is a polycrystalline silicon or an amorphous silicon, and said metal is tungsten, aluminum or metal including at least one of tungsten, aluminum and titanium.