Parameter variation probing technique

• US 6,535,013 B2
• Filed: 12/28/2000
• Issued: 03/18/2003
• Est. Priority Date: 12/28/2000
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Samaan, Samie B.
• Primary Examiner(s): Cuneo, Kamand
• Assistant Examiner(s): Nguyen, Tung X.
• Application Number:
  US09/749,433
• Publication Number:
  US 20020084797A1
• Time in Patent Office: 810 Days
• Field of Search: 324/765, 324/763, 324/755, 439/66-70, 368/101-123, 714/733, 714/734, 257/48, 331/65, 331/57
• US Class Current: 324/750.3
• CPC Class Codes: G01R 31/3016 Delay or race condition test, e.g. race hazard test
• CPC Class Codes: G01R 31/31858 Delay testing

Abstract

A technique for probing parameter variations in an integrated circuit chip includes providing a group of ring oscillators disposed over the integrated circuit chip, each oscillator producing an output representative of an integrated circuit chip parameter or group of parameter. A controller is provided to selectively enable one of the group of ring oscillators and a multiplexer is provided to output an output of one of the group of ring oscillators enabled by the controller. Each ring oscillator may include a gated inverter, having an enable/disable input, connected to a group of inverters arranged in a ring, the total number of inverters being an odd number. The group of ring oscillators may include a shift register chain consisting of a group of shift registers, an output of each shift register being respectively connected to an enable/disable input of the gated inverter of one of the group of ring oscillators. The multiplexer may include an exclusive-OR gate having inputs respectively connected to an output of each of the group of ring oscillators. An inverter may be disposed between each output of the group of ring oscillators and its'"'"' respective input to the multiplexer.

Claims

1. An apparatus for probing parameter variations in an integrated circuit chip comprising:

a plurality of ring oscillators disposed over the integrated circuit chip, each oscillator, when enabled, producing an output representative of an integrated circuit chip parameter or group of parameters;

a controller connected to the plurality of ring oscillators to selectively enable one of the plurality of ring oscillators;

at least one daisy-chain output line having a path thereof disposed over the integrated circuit chip; and

a plurality of gating-devices to connect ones of the plurality of ring oscillators to the at least one daisy-chain output line at differing locations along the path thereof to daisy-chain the outputs from the plurality of ring oscillators, to provide an output thereof on the at least one daisy-chain output line.

2. The apparatus of claim 1, wherein each ring oscillator comprises a gated inverter having an enable/disable input and a plurality of inverters, the gated inverter and the plurality of inverters being arranged in a ring, the total number of inverters, including the gated inverter, being an odd number.

4. The apparatus of claim 1, wherein ones of the plurality of gating-devices comprise an exclusive-OR gate having inputs respectively connected to an output of ones of the plurality of ring oscillators.

5. The apparatus of claim 4, further comprising an inverter disposed between each output of the plurality of ring oscillators and its'"'"' respective input to a gating-device of the plurality of gating-devices.

6. The apparatus of claim 1, further comprising a frequency counter connected to an output of the at least one daisy-chain output line.

20. The apparatus of claim 2, wherein the plurality of ring oscillators comprise a shift register chain comprised of a plurality of shift registers, an output of each shift register being respectively connected to an enable/disable input of the gated inverter of one of the plurality of ring oscillators.

21. The apparatus of claim 6, further comprising a scan-out chain comprising flip-flops respectively connected to the frequency counter to output the number counted by the frequency counter.

3. An apparatus for probing parameter variations in an integrated circuit chip comprising:

a plurality of ring oscillators disposed over the integrated circuit chip, each oscillator, when enabled, producing an output representative of an integrated circuit chip parameter or group of parameters;

a controller connected to the plurality of ring oscillators to selectively enable one of the plurality of ring oscillators; and

a multiplexer connected to the plurality of ring oscillators to provide an output thereof;

wherein each ring oscillator comprises a gated inverter having an enable/disable input and a plurality of inverters, the gated inverter and the plurality of inverters being arranged in a ring, the total number of inverters, including the gated inverter, being an odd number; and

wherein the plurality of ring oscillators comprise a shift register chain comprised of a plurality of shift registers, an output of each shift register being respectively connected to an enable/disable input of the gated inverter of one of the plurality of ring oscillators.

22. The apparatus of claim 3, wherein the multiplexer comprises an exclusive-OR gate having inputs respectively connected to an output of each of the plurality of ring oscillators.

23. The apparatus of claim 3, further comprising a frequency counter connected to an output of the multiplexer.

24. The apparatus of claim 23, further comprising a scan-out chain comprising flip-flops respectively connected to the frequency counter to output the number counted by the frequency counter.

7. An apparatus for probing parameter variations in an integrated circuit chip comprising:

a plurality of ring oscillators disposed over the integrated circuit chip, each oscillator, when enabled, producing an output representative of an integrated circuit chip parameter or group of parameters;

a controller connected to the plurality of ring oscillators to selectively enable one of the plurality of ring oscillators; and

a multiplexer connected to the plurality of ring oscillators to provide an output thereof; and

a frequency counter connected to an output of the multiplexer, wherein the frequency counter comprises an input gate connected to a ripple counter, the input gate receiving the output of the multiplexer and also receiving a gate pulse of the predetermined width such that the output of the multiplexer is selectively inputted to the ripple counter by the gate pulse to enable the ripple counter to count to a number which is proportional to the frequency of the selectively enabled ring oscillator.

8. The apparatus of claim 7, further comprising a scan-out chain comprising flip-flops respectively connected to the ripple counter to output the number counted by the ripple counter.

9. A method of probing parameter variations in an integrated circuit chip comprising:

having a plurality of ring oscillators disposed over the integrated circuit chip, each oscillator, when enabled, producing an output representative of an integrated circuit chip parameter or group of parameters;

selectively enabling one of the plurality of ring oscillators;

having at least one daisy-chain output line having a path thereof disposed over the integrated circuit chip; and

having a plurality of gating-devices connect ones of the plurality of ring oscillators to the at least one daisy-chain output line at differing locations along the path thereof to daisy-chain the outputs from the plurality of ring oscillators, to provide an output thereof on the at least one daisy-chain output line.

25. The method of claim 9, comprising measuring a frequency of an output of the at least one daisy-chain output line to produce a measured frequency of an enabled ring oscillator, the measured frequency being representative of an integrated circuit chip parameter or group of parameters at a location of the enabled ring oscillator.

26. The method of claim 25, further comprising outputting the measured frequency as a digital output.

10. A method of probing parameter variations in an integrated circuit chip comprising:

having a plurality of ring oscillators disposed over the integrated circuit chip, each oscillator, when enabled, producing an output representative of an integrated circuit chip parameter or group of parameters;

selectively enabling one of the plurality of ring oscillators;

multiplexing outputs of the plurality of ring oscillators for providing an output thereof; and

measuring a frequency of the multiplexed output to produce a measured frequency of an enabled ring oscillator, the measured frequency being representative of an integrated circuit chip parameter or group of parameters at a location of the enabled ring oscillator.

11. The method of claim 10, further comprising outputting the measured frequency as a digital output.

12. The method of claim 10, further comprising outputting the measured frequency as a serial digital output.

13. An integrated circuit chip comprising an apparatus for probing parameter variations, the apparatus comprising:

a plurality of ring oscillators disposed over the integrated circuit chip, each oscillator, when enabled, producing an output representative of an integrated circuit chip parameter or group of parameters;

a controller connected to the plurality of ring oscillators to selectively enable one of the plurality of ring oscillators;

at least one daisy-chain output line having a path thereof disposed over the integrated circuit chip; and

a plurality of gating-devices to connect ones of the plurality of ring oscillators to the at least one daisy-chain output line at differing locations along the path thereof to daisy-chain the outputs from the plurality of ring oscillators, to provide an output thereof on the at least one daisy-chain output line.

14. The integrated circuit chip of claim 13, wherein each ring oscillator comprises a gated inverter having an enable/disable input and a plurality of inverters, the gated inverter and the plurality of inverters being arranged in a ring, the total number of inverters, including the gated inverter, being an odd number.

16. The integrated circuit chip of claim 13, wherein ones of the plurality of gating-devices comprise an exclusive-OR gate having inputs respectively connected to an output of ones of the plurality of ring oscillators.

17. The integrated circuit chip of claim 16, further comprising an inverter disposed between each output of the plurality of ring oscillators and its'"'"' respective input to a gating-device of the plurality of gating-devices.

18. The integrated circuit chip of claim 13, further comprising a frequency counter connected to an output of the at least one daisy-chain output line.

27. The integrated circuit chip of claim 13, wherein the plurality of ring oscillators comprise a shift register chain comprised of a plurality of shift registers, an output of each shift register being respectively connected to an enable/disable input of the gated inverter of one of the plurality of ring oscillators.

15. An integrated circuit chip comprising an apparatus for probing parameter variations, the apparatus comprising:

a plurality of ring oscillators disposed over the integrated circuit chip, each oscillator, when enabled, producing an output representative of an integrated circuit chip parameter or group of parameters;

a controller connected to the plurality of ring oscillators to selectively enable one of the plurality of ring oscillators; and

a multiplexer connected to the plurality of ring oscillators to provide an output thereof;

wherein each ring oscillator comprises a gated inverter having an enable/disable input and a plurality of inverters, the gated inverter and the plurality of inverters being arranged in a ring, the total number of inverters, including the gated inverter, being an odd number; and

wherein the plurality of ring oscillators comprise a shift register chain comprised of a plurality of shift registers, an output of each shift register being respectively connected to an enable/disable input of the gated inverter of one of the plurality of ring oscillators.

28. The integrated circuit chip of claim 15, wherein the multiplexer comprises an exclusive-OR gate having inputs respectively connected to an output of each of the plurality of ring oscillators.

29. The integrated circuit chip of claim 15, further comprising a frequency counter connected to an output of the multiplexer.

30. The integrated circuit chip of claim 29, further comprising a scan-out chain comprising flip-flops respectively connected to the frequency counter to output the number counted by the frequency counter.

19. An integrated circuit chip comprising an apparatus for probing parameter variations, the apparatus comprising:

a plurality of ring oscillators disposed over the integrated circuit chip, each oscillator producing an output representative of an integrated circuit chip parameter;

a controller connected to the plurality of ring oscillators to selectively enable one of the plurality of ring oscillators;

a multiplexer connected to the plurality of ring oscillators to provide an output thereof; and

a frequency counter connected to an output of the multiplexer, wherein the frequency counter comprises an input gate connected to a ripple counter, the input gate receiving the output of the multiplexer and also receiving a gate pulse of the predetermined width such that the output of the multiplexer is selectively inputted to the ripple counter by the gate pulse to enable the ripple counter to count to a number which is proportional to the frequency of the selectively enabled ring oscillator.

31. The integrated circuit chip of claim 19, further comprising a scan-out chain comprising flip-flops respectively connected to the ripple counter to output the number counted by the ripple counter.