Data bus fault detection circuit and method

• US 6,535,028 B1
• Filed: 11/12/2001
• Issued: 03/18/2003
• Est. Priority Date: 11/12/2001
• Status: Expired due to Fees

• Current Assignee: Deere & Company
• Original Assignee: Deere & Company
• Inventors: Baker, Keith Ronald
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): Luu, An T.
• Application Number:
  US09/986,810
• Time in Patent Office: 491 Days
• Field of Search: 327/63-65, 327/72, 327/74, 327/75, 327/76, 327/77, 701/36, 701/39
• US Class Current: 327/63
• CPC Class Codes: H03K 5/19 Monitoring patterns of pulse trains indicating amplitude G01R19/00; indicating frequency G01R23/00; measuring characteristics of individual pulses G01R29/02
• CPC Class Codes: H04L 1/24 Testing correct operation
• CPC Class Codes: H04L 25/08 Modifications for reducing interference; Modifications for reducing effects due to line faults ; Receiver end arrangements for detecting or overcoming line faults

Abstract

A receiver circuit is connected to a differential serial bus having first and second signal conductors. The receiver circuit includes a fault detection circuit which generates a difference signal representing a difference between a first signal on the first conductor and a second signal on the second conductors. A comparing circuit includes a plurality of comparators for comparing the difference signal, the first signal and the second signal to predetermined voltage levels. The comparing circuit also includes a plurality of logic units coupled to outputs of the comparators. A signal select circuit has a pair of inputs coupled to the first and second conductors, logic inputs coupled to logic outputs of the comparing circuit, and a signal output. The signal select circuit and the comparing circuit cooperate to control communication of the first and second conductors with the signal output as a function of fault conditions on the first and second conductors.

Claims

1. A fault detecting receiver circuit for connecting to a differential serial bus, the bus having first and second signal conductors, the receiver circuit comprising:

a fault detection circuit generating a difference signal representing a difference between a first signal on the first conductor and a second signal on the second conductor;

a comparing circuit comparing the difference signal, the first signal and the second signal to predetermined reference signals, the comparing circuit having a plurality of logic units, the logic units having logic outputs; and

a signal select circuit having a first input coupled to the first conductor, having a second input coupled to the second conductor, having logic inputs coupled to the logic outputs of the comparing circuit, and having a signal output, the signal select circuit and the comparing circuit cooperating to control communication of the first and second conductors with the signal output as a function of fault conditions on the first and second conductors.

2. The receiver circuit of claim 1, wherein:

the fault detection circuit comprises a pair of difference units.

3. The receiver circuit of claim 2, wherein:

the fault detection circuit further comprises a peak detector coupled between one of the difference units and the comparing circuit.

4. The receiver circuit of claim 1, wherein the comparing circuit comprises:

a first comparator having a first input which receives the difference signal and a second input which receives a first reference voltage;

a second comparator having a first input which receives a second reference voltage and a second input which receives the first signal;

a third comparator having a first input which receives the first signal and a second input which receives a third reference voltage;

a fourth comparator having a first input which receives the second signal and a second input which receives the third reference voltage;

a fifth comparator having a first input which receives the second reference voltage and a second input which receives the second signal; and

a sixth comparator having a first input which receives the difference signal and a second input which receives the first reference voltage.

5. The receiver circuit of claim 4, further comprising:

a first AND gate having an output, a first input coupled to an output of the second comparator, and a second input coupled to an output of the sixth comparator;

a second AND gate having an output, a first input coupled to a reference voltage, and a second input coupled to an output of the third comparator;

a third AND gate having an output, a first input coupled to the reference voltage, and a second input coupled to an output of the fourth comparator;

a fourth AND gate having an output, a first input coupled to an output of the first comparator, and a second input coupled to an output of the fifth comparator;

a first OR gate having an output, a first input coupled to the output of the first AND gate, and a second input coupled to the output of the second AND gate;

a second OR gate having an output, a first input coupled to the output of the third AND gate, and a second input coupled to the output of the fourth AND gate; and

a NOR gate having an output, a first input coupled to the output of the first OR gate, and a second input coupled to the output of the second OR gate.

6. The receiver circuit of claim 5, further comprising:

a first delay circuit coupled between the output of the first OR gate and the first input of the NOR gate; and

a second delay circuit coupled between the output of the second OR gate and the second input of the NOR gate.

7. The receiver circuit of claim 6, wherein the signal select circuit comprises:

a first comparator having an output, a first input coupled to the first conductor via a high pass filter and having a second input connected to a reference voltage;

a second comparator having an output, a first input coupled to the second conductor via a high pass filter and having a second input connected to the reference voltage;

a first inverter coupled to the output of the first comparator;

a second inverter coupled to the output of the second comparator;

a first AND gate having an output, a first input coupled to an output of the first inverter, and a second input coupled to an output of the second inverter;

a second AND gate having an output, a first input coupled to the output of the first inverter, and a second input coupled to the output of the second OR gate;

a third AND gate 86 having an output, a first input coupled to the output of the first AND gate of the signal select circuit, and a second input coupled to an output of the NOR gate;

a fourth AND gate having an output, a first input coupled to the output of the second inverter, and a second input coupled to the output of the first OR gate; and

an output OR gate having an output, a first input coupled to the output of the second AND gate of the signal select circuit, a second input coupled to the output of the third AND gate of the signal select circuit, and a third input coupled to the output of the fourth AND gate of the signal select circuit.

8. The receiver circuit of claim 1, wherein the signal select circuit comprises:

a first comparator having an output, a first input coupled to the high signal conductor via a high pass filter and having a second input connected to a reference voltage;

a second comparator having an output, a first input coupled to the low signal conductor via a high pass filter and having a second input connected to the reference voltage;

a first inverter coupled to the output of the first comparator;

a second inverter coupled to the output of the second comparator;

a first AND gate having an output, a first input coupled to an output of the first inverter, and a second input coupled to an output of the second inverter;

a second AND gate having an output, a first input coupled to the output of the first inverter, and a second input coupled to an output of the comparing circuit;

a third AND gate 86 having an output, a first input coupled to the output of the first AND gate, and a second input coupled to an output of the comparing circuit;

a fourth AND gate having an output, a first input coupled to the output of the second inverter, and a second input coupled to an output of the comparing circuit; and

an OR gate having an output, a first input coupled to the output of the second AND gate, a second input coupled to the output of the third AND gate, and a third input coupled to the output of the fourth AND gate.

9. The receiver circuit of claim 1, wherein the fault detection circuit comprises:

a first summing unit having an output, having a first input coupled to the first signal conductor, and having a second input connected to a negative reference voltage;

a second summing unit having an output, having a first input coupled to the second signal conductor and having a second input connected to a positive reference voltage;

a first difference unit having an output, having a plus input coupled to the output of the first summing unit and having a minus input coupled to the output of the second summing unit;

a second difference unit having an output, having a minus input coupled to the output of the first summing unit and having a plus input coupled to the output of the second summing unit.

10. The receiver circuit of claim 9, wherein the fault detection circuit further comprises:

a peak detector coupled between the output of the first difference unit and the comparing circuit.

11. The receiver circuit of claim 1, wherein the comparing circuit comprises:

a plurality of comparators, the comparators comparing the difference signal, the first signal and the second signal to predetermined reference signals, the plurality of logic units being coupled to outputs of the comparators.

12. A receiver circuit for connecting to a differential serial bus, the bus having a high signal conductor and a low signal conductor, the receiver circuit comprising:

a fault detection circuit generating a difference signal representing a difference between the high signal and the low signal;

a comparing circuit having a plurality of comparators, the comparing circuit comparing the difference signal, the high signal and the low signal to predetermined voltage levels; and

a signal select circuit having a first input coupled to the high signal conductor, having a second input coupled to the low signal conductor having a signal output, and having a plurality of gates coupled between the first and second inputs and the signal output, the gates also being coupled to the comparing circuit, the signal select circuit and the comparing circuit cooperating to communicate a differential signal from the bus to the signal output when no faults occur, to communicate only the high signal to the signal output when a fault is associated with the low signal, to communicate only the low signal to the signal output when a fault is associated with the high signal, and to communicate a fault signal to the signal output when faults are associated with both the low and high signal.

13. A receiver circuit for connecting to a differential serial bus, the bus having first and second signal conductors, the receiver circuit comprising:

a first circuit generating a first signal representing a signal on the first conductor, a second signal representing a signal on the second conductor, and generating a difference signal representing a difference between a first signal and the second signal;

a second circuit generating fault output signals as a function of the difference signal, the first signal and the second signal; and

a third circuit coupled to the second circuit and coupled to the first and second conductors, the third circuit controlling communication of the first and second conductors to a signal output as a function of fault output signals.

14. A method of detecting faults on a differential serial bus, the bus having first and second signal conductors, the method comprising:

generating a difference signal representing a difference between a first signal on the first conductor and a second signal on the second conductor;

comparing the difference signal, the first signal and the second signal to predetermined reference signals; and

controlling communication of the first and second signals as a function of results of the comparing step.

15. The method of claim 14, further comprising:

detecting a peak value of the difference signal;

comparing the peak value to a reference level; and

controlling communication of the first and second signals also as a function of results of comparing the peak value to a reference level.

16. The method of claim 14, further comprising:

comparing the difference signal with a first reference voltage;

comparing the first signal with a second reference voltage;

comparing the first signal with a third reference voltage;

comparing the second signal with the third reference voltage;

comparing the second signal with the second reference voltage; and

comparing the difference signal with the first reference voltage.

17. The method of claim 16, further comprising:

performing a first AND operation on a result of comparing the first signal with the second reference voltage and on a result of comparing the difference signal with the first reference voltage;

performing a second AND operation on a reference voltage and on a result of comparing the first signal with the third reference voltage

performing a third AND operation on the reference voltage and on a result of comparing the second signal with the third reference voltage

performing a fourth AND operation on a result of comparing the difference signal with the first reference voltage and on a result of comparing the second signal with the second reference voltage;

performing a first OR operation on a result of the first AND operation and on a result of the second AND operation;

performing a second OR operation on a result of the third AND operation and on a result of the fourth AND operation; and

performing a NOR operation on a result of the first OR operation and on a result of the second OR operation.

18. The method of claim 17, further comprising:

performing a first delay operation between the first OR operation and the NOR operation; and

performing a second delay operation between the second OR operation and the NOR operation.

19. The method of claim 18, further comprising:

filtering the first signal with a high pass filter;

comparing the filtered first signal with a reference voltage;

filtering the second signal with a high pass filter;

comparing the filtered second signal with the reference voltage;

performing a first inverting operation upon a result of comparing the filtered first signal with the reference voltage;

performing second inverting operation upon a result of comparing the filtered second signal with the reference voltage;

performing a fifth AND operation 82 on results of the first and second inverting operations;

performing a sixth AND operation on a result of the first inverting operation, and on a result of the second OR operation;

performing a seventh AND operation 86 on a result of the fifth AND operation and on a result of the NOR operation;

performing an eighth AND operation 88 on a result of the second inverting operation and on a result of the second OR operation; and

performing an output OR operation on a result of the sixth, seventh and eighth AND operations.