Differential comparator with offset correction

• US 6,535,030 B1
• Filed: 06/19/2001
• Issued: 03/18/2003
• Est. Priority Date: 06/19/2001
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Nix, Michael A.
• Primary Examiner(s): TRAN, TOAN V
• Application Number:
  US09/884,725
• Time in Patent Office: 637 Days
• Field of Search: 327/63, 327/65-67, 327/77, 327/89, 327/560-563, 330/253, 330/255, 330/258, 330/311
• US Class Current: 327/65
• CPC Class Codes: H03F 3/45753 using switching means, e.g. sample and hold
• CPC Class Codes: H03F 3/45771 using switching means
• CPC Class Codes: H03K 5/2481 with at least one differential stage
• CPC Class Codes: H03K 5/249 using clock signals

Abstract

A differential comparator having offset correction and common mode control providing stable op amp output that changes only due to the original inputs coming into the comparator. The difference comparator has increased common-mode difference tolerance, and large op-amp offset tolerance, as well as fast decision time.

Claims

1. An operational amplifier, comprising:

a main current control branch comprising a first differential pair of transistors, each of the pair of first differential transistors are coupled in series with a diode connected transistor, the gates of the first differential pair are connectable to receive input voltages;

an output branch comprising a pair of current mirror transistors each gate connected to a gate of one of the diode-connected transistors;

a gain branch comprising a second differential pair of transistors, each of the pair of second differential transistors are connected to a drain of one of the current mirror transistors and gate connected to one of the input voltages; and

a zeroing branch comprising,

a tail current transistor having its drain coupled to ground,

a third differential pair of transistors each connected between a gate of one of the diode connected transistors and the tail current transistor, each transistor of the third differential pair have a gate connected to a common mode reference voltage, and

a fourth differential pair of transistors each connected between a drain of one of the current mirror transistors and the tail current transistor, and gate connected to one of a positive and a negative offset input.

2. An operational amplifier, comprising:

a first differential pair of transistors, each of the pair of first differential transistors are coupled in series with a diode-connected transistor, the gates of the first differential pair are connectable to input voltages;

a pair of current mirror transistors each having a gate connected to a gate of one of the diode connected transistors;

a second differential pair of transistors, each of the pair of second differential transistors are connected to a drain of one of the current mirror transistors and gate connected to one of the input voltages;

a tail current transistor having its drain coupled to ground;

a third differential pair of transistors each connected between a gate of one of the diode-connected transistors and the tail current transistor, each of the third differential pair of transistors have a gate connected to a common mode reference voltage; and

a fourth differential pair of transistors each connected between a drain of one of the current mirror transistors and the tail current transistor, and gate connected to one of a positive and a negative offset input.

3. A method of controlling a differential amplifier, comprising:

generating amplified first and second output currents in response to first and second input signals using a differential current mirror circuit, wherein the differential current mirror circuit comprises a first pair of input transistors coupled to a tail current transistor, and a first and second mirror transistors coupled to output nodes;

adjusting the first and second output current using a second pair of input transistors coupled to the output nodes to further amplify the output currents;

adjusting output voltages at the output nodes to have substantially zero offset; and

centering the output voltages to a common mode signal.