Programmable logic integrated circuit devices with low voltage differential signaling capabilities

• US 6,535,031 B1
• Filed: 05/13/2002
• Issued: 03/18/2003
• Est. Priority Date: 07/02/1998
• Status: Expired due to Term

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Wang, Bonnie I, Cliff, Richard G, Sung, Chiakang, Huang, Joseph, Wang, Xiaobao, Nguyen, Khai, Kim, In Whan, Yeung, Wayne
• Primary Examiner(s): TRAN, TOAN V
• Application Number:
  US10/146,438
• Time in Patent Office: 309 Days
• Field of Search: 327/65, 327/66, 330/253, 330/255, 330/257
• US Class Current: 327/65
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS
• CPC Class Codes: H03K 19/17744 for input/output signals
• CPC Class Codes: H03K 19/1778 Structural details for adapting physical parameters
• CPC Class Codes: H03K 19/17784 for supply voltage

Abstract

A programmable logic device is equipped for low voltage differential signaling (“LVDS”) by providing an LVDS input buffer and/or an LVDS output buffer on the device. I/O pins on the device that are used together in pairs for LVDS can alternatively be used individually for other types of signaling. The LVDS buffers are constructed to give good performance and to meet LVDS specifications despite variations due to temperature, manufacturing process inconsistency, and power supply changes.

Claims

1. Buffer circuitry configured to process a pair of signals, which collectively indicate information by the relative polarity of their voltages, comprising:

an NMOS differential stage connected to receive and process the signals;

a PMOS differential stage connected to receive and process the signals; and

an output stage responsive to outputs of both the NMOS differential stage and the PMOS differential stage to produce a single output signal indicative of the information, wherein the NMOS differential stage comprises first PMOS controlled source circuitry to increase output strength of the NMOS differential stage in response to voltages of the signals that are high enough to impair operation of the PMOS differential stage.

2. Buffer circuitry configured to process a pair of signals, which collectively indicate information by the relative polarity of their voltages, comprising:

an NMOS differential stage connected to receive and process the signals;

a PMOS differential stage connected to receive and process the signals; and

an output stage responsive to outputs of both the NMOS differential stage and the PMOS differential stage to produce a single output signal indicative of the information, wherein the PMOS differential stage comprises first NMOS controlled source circuitry to increase output strength of the PMOS differential stage in response to voltages of the signals that are low enough to impair operation of the NMOS differential stage.

3. The buffer circuitry defined in claim 1 wherein the output strength of the NMOS differential stage changes proportionally to the amount of an NMOS stage current drawn by the first source circuitry.

4. The buffer circuitry defined in claim 3 wherein the first source circuitry comprises first transistor circuitry, and wherein the amount of the NMOS stage current drawn changes proportionally to the amount of current that flows through the first transistor circuitry.

5. The buffer circuitry defined in claim 4 wherein the first source circuitry further comprises second transistor circuitry, and wherein connections between the first transistor circuitry, the second transistor circuitry, and the output stage are such that when voltages of the signals are high enough to impair operation of the PMOS differential stage, a first current flows through the first transistor circuitry, and when voltages of the signals are not high enough to impair operation of the PMOS differential stage, a first portion of the first current flows through the first transistor circuitry, and a second portion of the first current flows through the second transistor circuitry.

6. The buffer circuitry defined in claim 5 wherein the first source circuitry further comprises PMOS detection circuitry coupled to the pair of signals and the second transistor circuitry, such that when voltages of the signals are high enough to impair operation of the PMOS differential stage, the PMOS detection circuitry disables the second transistor circuitry, and when voltages of the signals are not high enough to impair operation of the PMOS differential stage, the PMOS detection circuitry enables the second transistor circuitry.

7. The buffer circuitry defined in claim 5 wherein the first transistor circuitry is coupled between a source of relatively high voltage and a source of relatively low voltage.

8. The buffer circuitry defined in claim 7 wherein the second transistor circuitry is coupled between the source of relatively high voltage and the source of relatively low voltage.

9. The buffer circuitry defined in claim 1 further comprising programmable function control circuitry connected to selectively enable the first source circuitry.

10. The buffer circuitry defined in claim 4 further comprising programmable function control circuitry connected to selectively enable the first transistor circuitry.

11. The buffer circuitry defined in claim 1 wherein the PMOS differential stage comprises second source circuitry to increase output strength of the PMOS differential stage in response to voltages of the signals that are low enough to impair operation of the NMOS differential stage.

12. The buffer circuitry defined in claim 11 further comprising programmable function control circuitry connected to selectively enable the first source circuitry and the second source circuitry.

13. The buffer circuitry defined in claim 2 wherein the output strength of the PMOS differential stage changes proportionally to the amount of a PMOS stage current drawn by the first source circuitry.

14. The buffer circuitry defined in claim 13 wherein the first source circuitry comprises first transistor circuitry, and wherein the amount of the PMOS stage current drawn changes proportionally to the amount of current that flows through the first transistor circuitry.

15. The buffer circuitry defined in claim 14 wherein the first source circuitry further comprises second transistor circuitry, and wherein connections between the first transistor circuitry, the second transistor circuitry, and the output stage are such that when voltages of the signals are low enough to impair operation of the NMOS differential stage, a first current flows through the first transistor circuitry, and when voltages of the signals are not low enough to impair operation of the NMOS differential stage, a first portion of the first current flows through the first transistor circuitry, and a second portion of the first current flows through the second transistor circuitry.

16. The buffer circuitry defined in claim 15 wherein the first source circuitry further comprises NMOS detection circuitry coupled to the pair of signals and the second transistor circuitry, such that when voltages of the signals are low enough to impair operation of the NMOS differential stage, the NMOS detection circuitry disables the second transistor circuitry, and when voltages of the signals are not low enough to impair operation of the NMOS differential stage, the NMOS detection circuitry enables the second transistor circuitry.

17. The buffer circuitry defined in claim 15 wherein the first transistor circuitry is coupled between a source of relatively high voltage and a source of relatively low voltage.

18. The buffer circuitry defined in claim 17 wherein the second transistor circuitry is coupled between the source of relatively high voltage and the source of relatively low voltage.

19. The buffer circuitry defined in claim 2 further comprising programmable function control circuitry connected to selectively enable the first source circuitry.

20. The buffer circuitry defined in claim 14 further comprising programmable function control circuitry connected to selectively enable the first transistor circuitry.

21. The buffer circuitry defined in claim 2 wherein the NMOS differential stage comprises second source circuitry to increase output strength of the NMOS differential stage in response to voltages of the signals that are high enough to impair operation of the PMOS differential stage.

22. The buffer circuitry defined in claim 21 further comprising programmable function control circuitry connected to selectively enable the first source circuitry and the second source circuitry.