Device for encoding n-bit source words into corresponding m-bit channel words and decoding m-bit channel words into corresponding n-bit source words

• US 6,535,151 B2
• Filed: 03/20/2002
• Issued: 03/18/2003
• Est. Priority Date: 12/21/1998
• Status: Expired due to Fees

• Current Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Original Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Inventors: Coene, Willem M.J.
• Primary Examiner(s): WAMSLEY, PATRICK G
• Application Number:
  US10/102,358
• Publication Number:
  US 20020175842A1
• Time in Patent Office: 363 Days
• Field of Search: 341/58, 341/59, 341/95, 341/102, 341/107, 341/50, 341/51, 341/57, 375/286, 714/792
• US Class Current: 341/102
• CPC Class Codes: G11B 20/1426 conversion to or from block codes or representations thereof
• CPC Class Codes: H03M 5/145 Conversion to or from block codes or representations thereof

Abstract

A device is disclosed for encoding a stream of databits of a binary source signal (S) into a stream of databits of a binary channel signal (C), wherein the stream of databits of the source signal is divided into n-bit source words (x₁, x₂), which device comprises converting means (CM) conceived to convert said n-bit source words into corresponding m-bit channel words (y₁, y₂, y₃) in accordance with a conversion of the Jacoby type, where m and n are integers, with m>n. The device further comprises control means (10) for carrying out DC-control on said binary channel signal by introducing a freedom of choice in the source-to-channel conversion.

Furthermore, a decoding device is disclosed for decoding the channel signal obtained by means of the encoding device.

Claims

1. A device for encoding a stream of databits of a binary source signal (S) into a stream of databits of a binary channel signal (C), wherein the stream of databits of the source signal is divided into n-bit source words, which device comprises converting means (LC) conceived to convert said n-bit source words into corresponding in-bit channel words of the binary channel signal in accordance with a conversion of the Jacoby type, where m and n are integers, with m>

n, characterized in that the device further comprises control means for carrying out stochastic DC-control on said binary channel signal by introducing a freedom of choice in the source-to-channel conversion, wherein said introducing said freedom of choice limits a running digital sum (RDS) of the binary channel signal.

2. A device as claimed in claim 1, characterized in that said converting means (LC) are conceived to convert a block of p consecutive n-bit source words into a block of p consecutive in-bit channel words, at least one of the bits in said blocks of p consecutive in-bit channel words being either ‘

0’

or ‘

1’

under the influence of said control means, p being an integer which is larger than 1.

3. A device as claimed in claim 2, characterized in that, for p=3, n=2, m=3, the converting means (LC) are conceived to convert predetermined blocks of three consecutive 2-bit source words into blocks of three consecutive 3-bit channel words in accordance with the following table:

4. A device as claimed in claim 2, characterized in that, for p=3, n=2, m=3, the converting means (LC) are conceived to convert predetermined blocks of three consecutive 2-bit source words into blocks of three consecutive 3-bit channel words in accordance with the following table:

5. A device as claimed in claim 2, characterized in that, for p=4, n=2, m=3, the converting means (LC) are conceived to convert predetermined blocks of four consecutive 2-bit source words into blocks of four consecutive 3-bit channel words in accordance with the following table:

6. A device as claimed in claim 2, characterized in that, for p=4, n=2, m=3, the converting means (LC) are conceived to convert predetermined blocks of four consecutive 2-bit source words into blocks of four consecutive 3-bit channel words in accordance with the following table:

7. A device as claimed in claim 2, characterized in that, for p=4, n=2, m=3, the converting means (LC) are conceived to convert predetermined blocks of four consecutive 2-bit source words into blocks of four consecutive 3-bit channel words in accordance with the following table:

8. A device as claimed in claim 1, said device further comprising a first shift register whose input is adapted to receive said databits of the source signal and whose outputs are coupled to corresponding inputs of said converting means so to enable the first shift register to effectuate a series-parallel transmission of said databits of the source signal to said converting means.

9. A device as claimed in claim 8, said device further comprising a second shift register whose output is coupled to an output terminal and whose inputs are coupled to corresponding outputs of said converting means so to enable the second shift register to effectuate a parallel-series transmission of said databits of the binary channel signal from said converting means to said output terminal.

10. A device as claimed in claim 1, wherein n=2 and m=3, and said conversion of the Jacoby type comprises converting 2-bit source words into 3-bit channel words in accordance with the following table:

11. A device as claimed in claim 1, wherein said freedom of choice occurs at DC-control points in the binary channel signal, and wherein said occurrence of said DC-control points in the binary channel signal depends on the databits in the source signal.

12. A device as claimed in claim 1, wherein extra parity preserve bits are not utilized in said source-to-channel conversion.

13. A device as claimed in claim 1, wherein at least one zero is present between any two consecutive ones in the databits of the binary channel signal.

14. A device as claimed in claim 1, wherein n=2 and m=3.

16. A device as claimed in any one of the preceding claims, characterized in that the device further comprises precoding means for precoding the channel signal so as to obtain a precoded channel signal, and recording means for recording the precoded channel signal onto a record carrier.

17. A device as claimed in claim 16, characterized in that said record carrier an optical record carrier.

18. A device as claimed in claim 16, characterized in that the device further comprises bit-adding means for carrying out additional DC-control.

19. A device as claimed in claim 16, wherein said record carrier is a magnetic record carrier.

15. A device for encoding a stream of databits of a binary source signal (S) into a stream of databits of a binary channel signal (C), wherein the stream of databits of the source signal is divided into n-bit source words, which device comprises converting means (LC) conceived to convert said source words into corresponding in-bit channel words in such a way that the m-bit channel words lack successive bits having a binary value that results in signal transitions, characterized in that the device further comprises control means for carrying out stochastic DC-control on said binary channel signal by introducing a freedom of choice in the source-to-channel conversion, wherein said introducing said freedom of choice limits a running digital sum (RDS) of the binary channel signal.

20. A method of encoding a stream of databits of a binary source signal (S) into a stream of databits of a binary channel signal (C), wherein the stream of databits of the source signal is divided into n-bit source words, said source words being converted into corresponding m-bit channel words in accordance with a conversion of the Jacoby type, where m and n are integers, with m>

n, characterized in that the method further carries out stochastic DC-control on the binary channel signal by introducing a freedom of choice in the source-to-channel conversion, wherein said introducing said freedom of choice limits a running digital sum (RDS) of the binary channel signal.

21. A method as claimed in claim 20, characterized in that a block of p consecutive n-bit source words is converted into a block of p consecutive m-bit channel words, one of the bits in said blocks of p consecutive m-bit channel words being chosen under the influence of said DC-control, p being an integer which is larger than 1.

22. A method as claimed in claim 20 or 21, characterized in that the method further comprises the step of precoding the channel signal (C) so as to obtain a precoded channel signal, and the step of recording the precoded channel signal onto a record carrier.

24. A method as claimed in claim 20, characterized in that the method further adds merging bits to said consecutive code words for carrying out additional DC-control.

23. A method as claimed in 22, characterized in that said record carrier is an optical record carrier.

25. A binary channel signal (C) comprising a stream of databits, converted from a binary source signal (S) comprising a stream of databits, wherein the stream of databits of the source signal comprises n-bit source words, the channel signal comprising in-bit channel words, each one of said in-bit channel words corresponding to one of said n-bit source words in accordance with a conversion of the Jacoby type, where m and n are integers, with m>

n, characterized in that, in said binary channel signal, a pair of blocks of p consecutive m-bit channel words, being convened from the same block of p consecutive n-bit source words, is present, the blocks of the pair differing from each other in the bit value at one bit position only in said blocks, p being an integer which is larger than 1, wherein the bit value at the one bit position is determined by a freedom of choice in the source-to-channel conversion, wherein the bit value at the one bit position is adapted to carry out stochastic DC-control on the binary channel signal, and wherein said freedom of choice limits a running digital sum (RDS) of the binary channel signal.

26. A signal as claimed in claim 25, characterized in that the signal further comprises merging bits added to said consecutive code words for carrying out additional DC-control.

27. A record carrier comprising a binary channel signal (C) comprising a stream of databits, converted from a binary source signal (S) comprising a stream of databits, wherein the stream of databits of the source signal comprises n-bit source words, the channel signal comprising m-bit channel words, each one of said m-bit channel words corresponding to one of said n-bit source words in accordance with a conversion of the Jacoby type, where m and n are integers, with m>

n, characterized in that, in said binary channel signal, a pair of blocks of p consecutive in-bit channel words, being converted from the same block of p consecutive n-bit source words, is present, the blocks of the pair differing from each other in the bit value at one bit position only in said blocks, p being an integer which is larger than 1, wherein the bit value at the one bit position is determined by a freedom of choice in the source-to-channel conversion, wherein the bit value at the one bit position is adapted to carry out stochastic DC-control on the binary channel signal, and wherein said freedom of choice limits a running digital sum (RDS) of the binary channel signal.

28. A device for decoding a stream of databits of a binary channel signal (C) into a stream of databits of a binary source signal (S), wherein the stream of databits of the channel signal is divided into m-bit channel words, which device comprises deconverting means (LC) conceived to deconvert said m-bit channel words into corresponding n-bit source words in accordance with a deconversion of the Jacoby type, where m and n are integers, with m>

n, characterized in that said deconverting means are also conceived to deconvert a channel sequence comprising pairs of blocks of p consecutive m-bit channel words into the same blocks of p consecutive n-bit source words, the pairs of blocks of p consecutive m-bit channel words differing from each other in the bit value at one bit position only in said blocks, p being an integer which is larger than 1, said bit value at the one bit position having a binary value of selected from the group consisting of zero and one, said selected binary value minimizing the running digital sum (RDS) of the binary channel signal.

29. A decoding device as claimed in claim 28, characterized in that said decoding is carried out in accordance with the following table:

30. A decoding device as claimed in claim 29, characterized in that said decoding is carried out in accordance with the following table:

31. A device as claimed in claim 28, wherein at least one zero is present between any two consecutive ones in the databits of the binary channel signal.

32. A device as claimed in claim 28, said device further comprising a detector circuit having outputs respectively coupled to corresponding inputs of the deconverting means, said detector circuit adapted to supply control inputs to the deconverting means, said deconversion being dependent upon said control inputs.