Low power cyclic A/D converter

• US 6,535,157 B1
• Filed: 09/07/2001
• Issued: 03/18/2003
• Est. Priority Date: 09/07/2001
• Status: Expired due to Term

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Garrity, Douglas, Rakers, Patrick L.
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): NGUYEN, LINH V
• Application Number:
  US09/949,245
• Time in Patent Office: 557 Days
• Field of Search: 341/161, 341/172, 341/155, 341/136, 341/163
• US Class Current: 341/163
• CPC Class Codes: H03M 1/403 using switched capacitors

Abstract

A low power cyclic RSD analog to digital converter (20) has a single RSD stage (22) that receives one of an analog input signal and a residual voltage feedback signal and converts the one selected signal to a digital output signal. The RSD stage (22) generates the residue voltage feedback signal. A first switch (32) is connected between a converter input terminal (30) and an input terminal of the RSD stage (22) for applying the analog input signal to the RSD stage input terminal. A second switch (52) is connected between an output terminal of the RSD stage (22) and the input terminal of the RSD stage. When the first switch (32) is closed, the second switch (52) is open so that the analog input signal is input to the RSD stage (22), and when the first switch (32) is open, the second switch (52) is closed so that the residual voltage feedback signal is input to the RSD stage (22). The RSD stage (22) includes a pair of comparators (34, 36) that compare the selected one of the analog input signal and the residual voltage feedback signal to predetermined high and low voltages, respectively. A logic circuit (38) connected to the comparators (34, 36) receives their outputs and generates the digital output signal based on these outputs. Use of a single stage and only two comparators conserves chip real estate.

Claims

1. A cyclic redundant signed digit (RSD) analog to digital converter, comprising:

an input terminal for receiving an analog input signal;

a single RSD stage connected to the input terminal for receiving a selected one of the analog input signal and a residual voltage feedback signal and converting the one selected signal to a digital output signal, wherein the RSD stage also generates the residual voltage feedback signal and returns the residual voltage feedback signal directly back to an input of the single RSD stage;

a first switch connected between the input terminal and the RSD stage for inputting the analog input signal to the RSD stage; and

a feedback switch connected between the input of the single RSD stage and an output of the single RSD stage wherein when the feedback switch is closed, the first switch is open so that the residual voltage feedback signal is input to the single RSD stage, and when the first switch is closed, the feedback switch is open so that the analog input signal is input to the single RSD stage;

the RSD stage comprising;

a first comparator connected to the first switch for comparing the selected one of the analog input signal and the residual voltage feedback signal to a predetermined high voltage and providing a first comparator output signal;

a second comparator connected to the first switch for comparing the selected one of the analog input signal and the residual voltage feedback signal to a predetermined low voltage and providing a second comparator output signal; and

a logic circuit connected to the first and second comparator and receiving the first and second comparator output signals and generating the digital output signal based on the first and second comparator output signals.

2. The analog to digital converter of claim 1, wherein the logic circuit further generates high, mid and low switch control signals based on the first and second comparator output signals and wherein the RSD stage further comprises:

a gain block connected to the first switch and receiving the selected one of the analog input signal and the residual voltage feedback signal and generating a gain block output signal; and

an adder connected to the gain block and the first and second comparators, the adder generating the residual voltage feedback signal from one of the gain block output signal, a sum of the gain block output signal and a first reference voltage, and a sum of the gain block output signal and a second reference voltage, wherein the addition of the gain block output signal with one of the first and second reference voltages or a zero voltage is determined using the high, mid and low switch control signals.

3. The analog to digital converter of claim 2, further comprising:

a second switch connected between a first reference voltage source and the adder for selectively inputting the first reference voltage to the adder;

a third switch connected between a substantially zero voltage and the adder for selectively inputting the zero voltage to the adder; and

a fourth switch connected between a second reference voltage source and the adder for selectively inputting the second reference voltage to the adder, wherein the high, mid, and low switch control signals generated by the logic circuit respectively control the second, third and fourth switches.

4. The analog to digital converter of claim 3, wherein the first and second comparators operate at about two times the speed of the gain block and the adder.

5. A cyclic RSD analog to digital converter, comprising:

an input terminal for receiving an analog input signal;

a first switch connected between the input terminal and a first node for selectively applying the analog input signal to the first node;

a second switch connected between the first node and a second node for selectively applying a residual voltage feedback signal to the first node;

a first comparator connected to the first node for comparing a selected one of the analog input signal and the residual voltage feedback signal to a predetermined high voltage and generating a first comparator output signal;

a second comparator connected to the first node for comparing the selected one of the analog input signal and the residual voltage feedback signal to a predetermined low voltage and generating a second comparator output signal;

an operational amplifier having an input terminal coupled to the first node for receiving the selected one of the analog input signal and the residual voltage feedback signal, and an output terminal connected to the second node, wherein the operational amplifier generates the residual voltage feedback signal and applies it the second node;

a logic circuit connected to the first and second comparator and receiving the first and second comparator output signals and generating a digital output signal based on the first and second comparator output signal; and

wherein when the first switch is closed, the second switch is opened so that the analog input signal is applied to the first node, and when the first switch is open, the second switch is closed so that the residual voltage feedback signal is applied to the first node.

6. The cyclic RSD analog to digital converter of claim 5, wherein the logic circuit further generates high, mid, and low switch control signals based on the first and second comparator output signals.

7. The cyclic RSD analog to digital converter of claim 6, further comprising:

a first capacitor connected to the second node by way of a third switch and to the operational amplifier input terminal by way of a fourth switch;

a second capacitor connected to the operational amplifier input terminal by way of the fourth switch and to the first node by way of a fifth switch;

a sixth switch connected between a first reference voltage source and a third node located between the second capacitor and the fifth switch;

a seventh switch connected between a second reference voltage source and the third node; and

an eighth switch connected between a third reference voltage source and the third node.

8. The cyclic RSD analog to digital converter of claim 7, further comprising:

a third capacitor connected to the second node by way of an ninth switch and to the operational amplifier input terminal by way of a tenth switch, wherein a fourth node is defined at a point between the ninth switch and the third capacitor;

a fourth capacitor connected to the second node by way of an eleventh switch and to the operational amplifier input terminal by way of the tenth switch;

a twelfth switch connected between the second node and the fourth node; and

a thirteenth switch connected between the first node and a fifth node, the fifth node being located at a point between the third switch and the first capacitor.

9. The cyclic RSD analog to digital converter of claim 8, further comprising:

a fourteenth switch connected between the first reference voltage source and a sixth node located between the eleventh switch and the fourth capacitor; and

a fifteenth switch connected between the second reference voltage source and the fifth node; and

a sixteenth switch connected between the third reference voltage source and the fifth node.

10. The analog to digital converter of claim 9, wherein the first and second comparators operate at about two times the speed of the operational amplifier.