Multichip module substrates with buried discrete capacitors and components and methods for making

• US 6,535,398 B1
• Filed: 03/07/2000
• Issued: 03/18/2003
• Est. Priority Date: 03/07/2000
• Status: Expired due to Term

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Moresco, Larry L.
• Primary Examiner(s): Paladini, Albert W.
• Assistant Examiner(s): Vigushin, John B.
• Application Number:
  US09/519,713
• Time in Patent Office: 1,106 Days
• Field of Search: 361/734, 361/738, 361/760, 361/763, 361/766-768, 361/771, 361/780, 361/782-784, 361/803, 361/792-795, 361/744, 257/685, 257/686, 257/700, 257/723, 257/724, 174/256, 174/258-260
• US Class Current: 361/792
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/5385 Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/15192 Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/19105 in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/19106 in a mirrored arrangement on two different side of a common die mounting substrate
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H05K 1/023 using auxiliary mounted passive components or auxiliary substances printed passive components H05K1/16
• CPC Class Codes: H05K 1/185 Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit semiconductor chips encapsulated by interconnect and support structures H01L23/5389, H01L24/00
• CPC Class Codes: H05K 3/4644 by building the multilayer layer by layer, i.e. build-up multilayer circuits making via holes in the insulating layers H05K3/0011; special circuit boards as base or core whereon the multilayer is built H05K3/4602

Abstract

Modularly constructed multichip modules with are disclosed. A plurality of miniature capacitor substrates and/or miniature resistor substrates are assembled and attached to a base substrate, preferably in a regular pattern. Power supply substrates are preferably attached to the base substrate along with the miniature substrates. All of the attached components are preferably pretested and have thicknesses close to one another. The pretesting substantially increases the manufacturing yield. Gaps between the miniature substrates and power supply substrates are filled with a polymer material, such as a powder-filled polyimide precursor. Thereafter, dielectric layer is formed over the components to provide a more planar surface. The dielectric layer is preferably planarized, such as by a chemical mechanical polishing process, to provide for a more planar layer. Thereafter, a plurality of interleaving metal and dielectric layers are formed over the assembled components to provide power distribution planes and signal lines.

Claims

1. A multilayer interconnect module for interconnecting a plurality of integrated circuit chips, said module comprising:

a primary substrate having a top surface;

a plurality of secondary substrates, each secondary substrate having a top surface, a bottom surface, and at least one side between its top and bottom surfaces, each said bottom surface being attached to the top surface of said primary substrate, at least one of said secondary substrates having a discrete capacitor formed on its top surface, each discrete capacitor having a first terminal and a second terminal disposed at the top surface of its corresponding secondary substrate;

a plurality of gaps between the sides of said secondary substrates;

a body of polymeric material formed in said gaps and having a top surface above the top surface of said primary substrate;

a first dielectric layer formed over the top surfaces of said secondary substrates and said body of polymeric material;

a plurality of vias formed through said first dielectric layer, at least two vias being connected to corresponding terminals of one said discrete capacitor;

one or more additional dielectric layers formed over said first dielectric layer, each said additional dielectric layer having at least two vias formed therein;

a plurality of chip connection pads formed on the uppermost additional dielectric layer for interconnecting to the plurality of integrated circuit chips;

a first power supply line formed on at least one of said dielectric layers and connected to one of the terminals of one of said discrete capacitors through one of said vias formed through said first dielectric layer, said first power supply line further connected to one of said chip connection pads through at least one of said vias formed through one of said additional dielectric layers; and

a second power supply line formed on at least one of said dielectric layers and connected to the other of the terminals of said one of the discrete capacitors through another one of said vias formed through said first dielectric layer, said second power supply line further connected to another one of said chip connection pads through at least one of said vias formed through one of said additional dielectric layers.

2. The module of claim 1 wherein one of said secondary substrates comprises a resistor formed on the top surface of the substrate and having a first terminal and a second terminal;

and

wherein said module further comprises a signal line formed on at least one of said dielectric layers and connected to the first terminal of said resistor through one of said vias formed through said first dielectric layer, said signal line further connected to one of said chip connection pads through at least one of said vias formed through one of said additional dielectric layers.

3. The module of claim 1 wherein one of said secondary substrates comprises a power supply substrate having a first supply strip formed on the top surface of the substrate;

and

wherein said first power supply line is further connected to said first power supply strip through one of said vias formed through said first dielectric layer.

4. The module of claim 3 wherein said power supply substrate further has a second power supply strip formed on the top surface of the substrate;

and

wherein said second power supply line is further connected to said second power supply strip through one of said vias formed through said first dielectric layer.

5. The module of claim 3 wherein one of said secondary substrates comprises a resistor formed on the top surface of the substrate and having a first terminal and a second terminal;

and

wherein said module further comprises a signal line formed on at least one of said dielectric layers and connected to the first terminal of said resistor through one of said vias formed through said first dielectric layer, said signal line further connected to one of said chip connection pads through at least one of said vias formed through one of said additional dielectric layers.

6. The module of claim 5 wherein said first power supply line is further connected to said second terminal of said resistor through one of said vias formed through said first dielectric layer.

7. The module of claim 1 wherein a plurality of integrated circuit chips are mounted on said chip connection pads with their top surfaces facing the top surfaces of said secondary substrates.

8. The module of claim 1 wherein each secondary substrate has been tested prior to assembly of the module.

9. The module of claim 1 wherein the top surface of said body of polymeric material is within 50 μ

m of the top surface of at least one secondary substrate.

10. The module of claim 1 wherein said body of polymeric material comprises a polyimide filler material.

11. The module of claim 1 wherein said first dielectric layer is formed from a fluidized polyimide precursor which is deposited over the top surfaces of said secondary substrates and-said body of polymeric material.

12. The module of claim 1 wherein each said additional dielectric layers is formed from a fluidized polyimide precursor and has a thickness of less than 20 μ

m.

13. The module of claim 1 wherein said secondary substrates are attached to said primary substrate by a polyimide layer formed over the top surface of said primary substrate.

14. A multilayer interconnect module for interconnecting a plurality of integrated circuit chips, said module comprising:

a primary substrate having a top surface;

a plurality of secondary substrates, each secondary substrate having a top surface, a bottom surface, and at least one side between its top and bottom surfaces, each said bottom surface being attached to the top surface of said primary substrate, at least one of said secondary substrates having at least one discrete resistor formed on its top surface, each discrete resistor having a first terminal and a second terminal disposed at the top surface of its corresponding secondary substrate;

a plurality of gaps between the sides of said secondary substrates;

a body of polymeric material formed in said gaps and having a top surface above the top surface of said primary substrate;

a first dielectric layer formed over the top surfaces of said secondary substrates and said body of polymeric material;

a plurality of vias formed through said first dielectric layer, at least two vias being connected to corresponding terminals of one said discrete resistor;

one or more additional dielectric layers formed over said first dielectric layer, each said additional dielectric layer having at least two vias formed therein;

a plurality of chip connection pads formed on the uppermost additional dielectric layer for interconnecting to the plurality of integrated circuit chips;

a signal line formed on at least one of said dielectric layers and connected to the first terminal of a first one of said discrete resistors through one of said vias formed through said first dielectric layer, said signal line further connected to one of said chip connection pads through at least one of said vias formed through one of said additional dielectric layers; and

a first power supply line formed on at least one of said dielectric layers and connected to the second terminal of said first discrete resistor through one of said vias formed through said first dielectric layer, said first power supply line further connected to one of said chip connection pads through at least one of said vias formed through one of said additional dielectric layers.

15. The module of claim 14 wherein one of said secondary substrates comprises a power supply substrate having a first supply strip formed on the top surface of the substrate;

and

wherein said first power supply line is further connected to said first power supply strip through one of said vias formed through said first dielectric layer.

16. The module of claim 14 wherein a plurality of integrated circuit chips are mounted on said chip connection pads with their top surfaces facing the top surfaces of said secondary substrates.

17. The module of claim 14 wherein each secondary substrate has been tested prior to assembly of the module.

18. The module of claim 14 wherein the top surface of said body of polymeric material is within 50 μ

m of the top surface of at least one secondary substrate.

19. The module of claim 14 wherein said body of polymeric material comprises a polyimide filler material.

20. The module of claim 14 wherein said first dielectric layer is formed from a fluidized polyimide precursor which is deposited over the top surfaces of said secondary substrates and said body of polymeric material.

21. The module of claim 14 wherein each said additional dielectric layers is formed from a fluidized polyimide precursor and has a thickness of less than 20 μ

m.

22. The module of claim 14 wherein said secondary substrates are attached to said primary substrate by a polyimide layer formed over the top surface of said primary substrate.