Nonvolatile memory system

• US 6,535,422 B2
• Filed: 12/21/2001
• Issued: 03/18/2003
• Est. Priority Date: 12/28/2000
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi, Ltd., Hitachi ULSI Systems Company Limited (Hitachi, Ltd.)
• Inventors: Tamura, Takayuki, Shiota, Shigemasa, Goto, Hiroyuki, Nakamura, Yasuhiro, Shibuya, Hirofumi
• Primary Examiner(s): PHAN, TRONG Q
• Application Number:
  US10/023,882
• Publication Number:
  US 20020085418A1
• Time in Patent Office: 452 Days
• Field of Search: 365/185.09, 365/185.11, 365/185.17, 365/185.33, 365/233, 365/52
• US Class Current: 365/185.11
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/20 Initialising; Data preset; Chip identification
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

The present invention provides a nonvolatile memory system whose storage capacity can be easily changed. The nonvolatile memory system comprises plural memory modules, a controller for controlling the operation of the plural memory modules according to access requests from the outside, and a module selecting decoder for selectively enabling the memory modules by decoding a selection signal outputted from the controller, wherein the memory modules are freely mounted or dismounted. With this arrangement, the storage capacity can be changed by increasing or decreasing the memory modules.

Claims

1. A nonvolatile memory system, comprising:

one or more memory modules each including a first control logic and one or more nonvolatile memories;

a controller for controlling at least one operation of each of the memory modules according to external access requests and for outputting a selection signal; and

a module selecting decoder that generates a module enable signal for selectively enabling at least one of the memory modules by decoding a first portion of the selection signal outputted from the controller,

wherein in a memory module not enabled by the module enable signal, a corresponding first control logic prevents at least one operation signal sent from the controller for activating said at least one operation from entering into the nonvolatile memories therein.

2. The nonvolatile memory system according to claim 1, wherein the memory modules each further includes:

a nonvolatile memory selecting decoder for decoding a second portion of the selection signal outputted from the controller thereby generating an output signal; and

a second control logic that forms a nonvolatile memory selection signal for selectively enabling at least one of the nonvolatile memories, based on an output enable signal of the controller and the output signal of the nonvolatile memory selecting decoder.

3. The nonvolatile memory system according to claim 1, further comprising a reset control unit that selectively and sequentially resets at least two of the memory modules in accordance with a reset signal from the controller.

4. The nonvolatile memory system according to claim 1, further comprising a reset control unit that selectively and sequentially resets at least two of the memory modules so as to reset each of the nonvolatile memories therein in accordance with a reset signal from the controller.

5. The nonvolatile memory system according to claim 3,

wherein the reset control unit includes information holding means having an output terminal corresponding to an input terminal for transmitting the reset signal from the controller to each of the memory modules, and

wherein the reset signal is successively negated by a updating signal from the controller to the information holding means.

6. The nonvolatile memory system according to claim 5, wherein the controller comprises:

a memory control unit that enables write interleave concurrently with write operations into at least two of the plural nonvolatile memories, transfers write data to other nonvolatile memories; and

a micro processing unit for controlling the operation of the entire controller.

7. The nonvolatile memory system according to claim 1, wherein the first control logic includes a corresponding logic gate for each said at least one operation signal.

8. The nonvolatile memory system according to claim 7, wherein the corresponding logic gate is a OR gate.

9. The nonvolatile memory system according to claim 1, wherein said at least one operation signal is one of a commend data signal, an output enable signal, a write enable signal and a serial clock signal.

10. The nonvolatile memory system according to claim 2, wherein the second control logic is a transceiver for controlling data transfer directions between the controller and the corresponding memory module.

11. The nonvolatile memory system according to claim 10, wherein the transceiver includes a pair of tri-state buffers and a pair of logic gates.

12. The nonvolatile memory system according to claim 5, wherein the information holding means includes a flip-flop circuit.

13. The nonvolatile memory system according to claim 5, wherein the information holding means includes a shift register.