ATM communication system interconnect/termination unit

• US 6,535,512 B1
• Filed: 03/07/1996
• Issued: 03/18/2003
• Est. Priority Date: 03/07/1996
• Status: Expired due to Term

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Daniel, Thomas, Nattkemper, Dieter, Varma, Subir
• Primary Examiner(s): BNIMOUSSA, ABDELHAMID
• Application Number:
  US08/614,803
• Time in Patent Office: 2,567 Days
• Field of Search: 370/395.1, 370/905, 370/908, 370/902, 370/901, 370/912, 370/389, 370/399, 370/442, 370/347, 370/465, 370/401, 370/351, 370/352, 370/428, 370/229, 370/230, 379/220.01, 379/240, 379/225, 379/224, 348/14.01, 348/14.11
• US Class Current: 370/395.1
• CPC Class Codes: H04L 12/5601 Transfer mode dependent, e.g. ATM
• CPC Class Codes: H04L 2012/5615 Network termination, e.g. NT1, NT2, PBX
• CPC Class Codes: H04L 2012/5618 Bridges, gateways [GW] or interworking units [IWU]

Abstract

An asynchronous transfer mode (ATM) digital electronic communication system includes an ATM communication system interconnection and termination unit (ATMCSI/TU). This ATMCSI/TU includes both a programmable microprocessor and several hardware-implemented coprocessors. The hardware-implemented coprocessors are under control of the microprocessor, and are dedicated to the performing of repetitive tasks. Thus, the microprocessor is freed to perform supervisory tasks in the ATM in addition to performing tasks associated with actual communication of digital data packages (i.e., CS-PDU'"'"'s) in the ATM system. Thus, the APU is freed from doing repetitive data manipulation tasks, while these tasks are performed by one or more hardware-implemented coprocessors using memory mapped data structures and linked lists of data.

Claims

1. An asynchronous transfer mode (ATM) communication device for use in an ATM communication system network, said device comprising:

memory means;

a scheduler processor permanently pre-configured to maintain in said memory means a calendar-based scheduler table having entries of virtual connections (VC'"'"'s) to be serviced in sequential cell slot time intervals to receive conversion sublayer protocol data units (CS-PDU'"'"'s);

a programmable processor servicing VC'"'"'s according to said calendar-based scheduler table, and said programmable processor including means for maintaining a hierarchical calendar including at least two recirculating arrays of linked descriptors, said hierarchical calendar having a first array of size N segments (where N is an integer), and a first event pointer moving step-wise from one segment of said first array to the next segment in a time equal to one cell slot time interval;

said hierarchical calendar including at least a second array of size M segments (in which M is an integer), and a respective second event pointer moving step-wise from one segment of said second array to the next segment in a time equal to N multiplied by T (where T is a single cell slot time interval).

2. The ATM communication device of claim 1 wherein N is equal to 353.

3. The ATM communication device of claim 1 wherein M is equal to 1000.

4. The ATM communication device of claim 1 wherein said pre-configured scheduler processor also includes internal register means for maintaining a copy of certain characteristics of VC'"'"'s being serviced and to be serviced, said certain characteristics including:

Buffer—

a pointer to a buffer memory location descriptor for a VC to be serviced or in service;

Present Buffer—

a pointer to a buffer memory location for a VC in service; and

current Virtual Circuit Descriptor (current VCD)—

a pointer to the current virtual circuit being serviced.

5. The ATM communication device of claim 1 wherein said programmable processor further exercised executive control over said scheduler processor to operate the latter in one of two selected modes of operation, said two selected modes of operation including:

flat rate mode, and priority mode.

6. The ATM communication device of claim 5 wherein said programmable processor causes said scheduler processor in said flat rate mode to internally save two sets of linked list pointers, one of said two sets of linked list pointers being a head end list including pointers to the head end of a linked list of VCD'"'"'s to be serviced in a particular cell slot time interval, the other of said two sets of linked list pointers being a tail end list including pointers to the tail end of a linked list of VCD'"'"'s to be serviced in a particular cell slot time interval.

7. The ATM communication device of claim 6 wherein said programmable processor causes said scheduler processor in said priority mode to internally save a set of linked list pointers to the head end of a linked list of VCD'"'"'s to be serviced in a particular cell slot time interval.

8. The ATM communication device of claim 6 wherein said programmable processor further exercised executive control over said scheduler processor to operate the latter in one of three classes of service for VC'"'"'s to be serviced, said classes of service including constant bit rate (CBR) service, available bit rate (ABR) service, and variable bit rate (VBR) service.

9. A data-structure driven asynchronous transfer mode (ATM) communication device for receiving, processing, and transmitting a plurality of data cells in an ATM communication system network, said device comprising:

memory means for receiving, storing and recovering ATM conversion sublaver protocol data units (CS-PDU'"'"'s), data-structures of linked lists with memory address pointers to starting and ending memory addresses as well as internal memory address pointers to successive elements of said data structures of linked lists by memory addresses in succession and regression, and calendar entries;

a scheduler processor permanently pre-configured to maintain a calendar-based scheduler table having entries of virtual connections (VC'"'"'s) to be serviced in sequential cell slot time intervals to receive CS-PDU'"'"'s from said memory means;

a programmable processor servicing VC'"'"'s according to said calendar-based scheduler table, and said programmable processor including means for maintaining a hierarchical calendar including at least two recirculating arrays of linked descriptors, said hierarchical calendar having. a first array of size N segments (where N is an integer), and a first event pointer moving step-wise from one segment of said first array to the next segment in a time equal to one cell slot time interval;

said hierarchical calendar including at least a second array of size M segments (in which M is an integer), and a respective second event pointer moving step-wise from one segment of said second array to the next segment in a time equal to N multiplied by T (where T is a single cell slot time interval).

10. The ATM communication device of claim 9 wherein said device further includes a pre-configured timer having means for maintaining plural hardware-implemented timers accessible to said pre-configured scheduler processor to measure said cell slot time intervals and schedule VC services therein.

11. The ATM communication device of claim 10 wherein said device further includes a permanently pre-configured direct memory access processor configured to segment and reassemble ATM CS-PDU'"'"'s respectively for storage in and stored in said memory means, and using said memory address pointers to recover and reassemble said CS-PDU'"'"'s.

12. The ATM communication device of claim 10 wherein said calendar-based scheduler table includes an entry for each cell time slot having a list of VC'"'"'s to be serviced in the particular cell time slot time interval.

13. The ATM communication device of claim 10 wherein said pre-configured scheduler processor includes internal register means for maintaining a copy of certain characteristics of VC'"'"'s being serviced and to be serviced, said certain characteristics including:

Next Head—

a pointer to the head end of a linked lists o f VC'"'"'s next to be serviced;

Previous Tail—

a pointer to the tail end of a linked list of VC'"'"'s last serviced;

Schd Class—

the class of service scheduled; and

Next Class—

the class of service next scheduled after the current class of VC'"'"'s to be serviced.

14. The ATM communication device of claim 10 wherein said pre-configured scheduler processor includes internal register means for maintaining a copy of certain characteristics of VC'"'"'s being serviced and to be serviced, said certain characteristics including:

Buffer—

a pointer to a buffer memory location descriptor for a VC to be serviced or in service;

Present Buffer—

a pointer to a buffer memory location for a VC in service; and

current Virtual Circuit Descriptor (current VCD)—

a pointer to the current virtual circuit being serviced.

15. The ATM communication device of claim 10 wherein said programmable processor further exercised executive control over said scheduler processor to operate the latter in one of two selected modes of operation, said two selected modes of operation including:

flat rate mode, and priority mode.

16. The ATM communication device of claim 15 wherein said programmable processor causes said scheduler processor in said flat rate mode to internally save two sets of linked list pointers, one of said two sets of linked list pointers being a head end list including pointers to the head end of a linked list of VCD'"'"'s to be serviced in a particular cell slot time interval, the other of said two sets of linked list pointers being a tail end list including pointers to the tail end of a linked list of VCD'"'"'s to be serviced in a particular cell slot time interval.

17. The ATM communication device of claim 15 wherein said programmable processor causes said scheduler processor in said priority mode to internally save a set of linked list pointers to the head end of a linked list of VCD'"'"'s to be serviced in a particular cell slot time interval.

18. The ATM communication device of claim 15 wherein said programmable processor further exercised executive control over said scheduler processor to operate the latter in one of three classes of service for VC'"'"'s to be serviced, said classes of service including constant bit rate (CBR) service, available bit rate (ABR) service, and variable bit rate (VBR) service.

19. A method for receiving, processing, and transmitting a plurality of data cells in an asynchronous transfer mode (ATM) communication system network, said method comprising:

providing memory means;

providing a scheduler processor, and permanently pre-configuring said scheduler processor to maintain in said memory means a calendar-based scheduler table having entries of virtual connections (VC'"'"'s) to be serviced in sequential cell slot time intervals to receive conversion sublayer protocol data units (CS-PDU'"'"'s);

providing a programmable processor, and utilizing said programmable processor to service VC'"'"'s according to said calendar-based scheduler table, including in said programmable processor means for maintaining a memory-efficient hierarchical calendar including at least two recirculating arrays of linked descriptors, causing said hierarchical calendar to have a first array of size N segments (where N is an integer), and a first event pointer moving step-wise from one segment of said first array to the next segment in a time equal to one cell slot time interval;

providing for said hierarchical calendar to include at least a second array of size M segments (in which M is an integer), and a respective second event pointer moving step-wise from one segment of said second array to the next segment in a time equal to N multiplied by T (where T is a single cell slot time interval).

20. The method of claim 19 further including the step of making N equal to 353.

21. The method of claim 19 further including the step of making M equal to 1000.

22. The method of claim 19 further including the step of causing said scheduler processor to internally save a set of linked list pointers to the head end of a linked list of virtual circuit descriptors (VCD'"'"'s) to be serviced in a particular cell slot time interval.