Detection and exploitation of cache redundancies

• US 6,535,584 B1
• Filed: 08/06/1999
• Issued: 03/18/2003
• Est. Priority Date: 11/12/1997
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Reinders, James
• Primary Examiner(s): Peikari, B. James
• Application Number:
  US09/370,093
• Time in Patent Office: 1,320 Days
• Field of Search: 711/133, 711/159, 711/122, 379/88.1, 714/6, 707/101, 710/68, 712/33, 712/300
• US Class Current: 379/88.1
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/0813 with a network or matrix configuration
• CPC Class Codes: G06F 12/0897 with two or more cache hierarchy levels with multilevel cache hierarchies G06F12/0811
• CPC Class Codes: G06F 2212/401 Compressed data

Abstract

A method and apparatus are provided for reducing the number of cache line data transfers among components of a computer system, thus reducing the amount of traffic on a bus and increasing overall system performance. A sideband communication line is provided to transfer information from a source cache agent pertaining to redundant data strings occurring in a cache line to a destination cache agent. If redundant data strings occur in a cache line, the transfer of one or more portions of a cache line from the source to the destination can be canceled. Redundancy logic is provided to detect occurrences of redundant data strings located in a given cache line, generate and transfer redundancy bits when predetermined redundant data strings occur and decode redundancy bits at a destination cache agent to determine whether redundant data strings occur in subsequent cache lines to be transferred. The components benefiting from this invention can include a processor with its own on-chip L1 cache, a L2 or L3, an I/O controller or any other component that can perform cache functions. Alternative embodiments are provided of redundancy logic operating in parallel with data and instruction busses as well as redundancy logic operations occurring serially with the data and instruction busses.

Claims

1. A computer system comprising:

a processor to process data;

a system bus coupled to the processor;

a cache agent coupled to the system bus; and

a redundancy circuit including a first redundancy circuit coupled to the cache agent, a second redundancy circuit coupled to the processor and a sideband communication line to communicate redundancy information between the processor and the cache agent representing a redundancy signal to indicate whether redundant portions of data occur in, a string of data.

2. The computer system according to claim 1, wherein the redundancy circuit further comprises a list of predetermined portions of redundant data.

3. The computer system according to claim 1, wherein the processor further comprises an L1 internal cache memory and wherein the first redundancy circuit is located in the L1 cache to generate the redundancy signal to indicate whether redundant data strings occur in the string of data located in the cache memory and the second redundancy circuit is located internal to the processor.

4. The computer system according to claim 1, further comprising a cache memory located external to the processor and wherein the first redundancy circuit is coupled to the cache memory, the second redundancy circuit is coupled to the processor and the sideband communication line transfers redundancy information between the processor and the cache memory.

5. The computer system according to claim 1, wherein a cache memory is coupled to the system bus and wherein the first redundancy circuit is coupled to the cache memory, the second redundancy circuit is coupled to a memory control and the sideband communication line to communicate redundancy information between the memory control and the cache memory.

6. The computer system according to claim 1, wherein a cache memory is coupled to the system bus and wherein the first redundancy circuit is coupled to the cache memory, the second redundancy circuit is coupled to the processor and the sideband communication line transfers redundancy information between the processor and the cache memory.

7. The computer system according to claim 1, wherein a cache memory is coupled to the system bus and wherein the first redundancy circuit is coupled to a memory control, the second redundancy circuit is coupled to the processor and the sideband communication line transfers redundancy information between the processor and the memory control.

8. A processor comprising:

an internal cache memory;

a cache bus to transfer portions of data between the internal cache memory and other locations;

redundancy logic to determine whether portions of data to be transferred are redundant; and

a sideband communication line to transfer redundancy information indicating whether redundant data occurs in a portion of data.

9. The processor of claim 8, wherein the redundancy logic includes a first redundancy circuit coupled to a cache agent, a second redundancy circuit coupled to the processor and the sideband communication line to transfer redundancy information between the processor and the cache agent.

10. The processor according to claim 8, wherein the redundancy logic further comprises a list of predetermined portions of redundant data.

11. The processor according to claim 8, wherein the processor further comprises an L1 internal cache memory and wherein the redundancy logic includes a first redundancy circuit located in the L1 cache to generate a redundancy signal to indicate whether redundant data strings occur in a string of data located in the cache memory and comprises a second redundancy circuit located internal to the processor, and the sideband communication line is coupled with the processor and the L1 cache.

12. The processor according to claim 8, further comprising a cache memory located external to the processor and wherein the redundancy logic includes a first redundancy circuit coupled to a cache memory, a second redundancy circuit coupled to the processor and the sideband communication line is coupled with the processor and the cache memory.

13. The processor according to claim 8, wherein a cache memory is coupled to the cache bus and wherein the redundancy logic includes a first redundancy circuit coupled to the cache memory, a second redundancy circuit coupled to a memory control and the sideband communication line is coupled with the memory control and the cache memory.

14. The processor according to claim 8, wherein a cache memory is coupled to the cache bus and wherein the redundancy logic includes a first redundancy circuit coupled to the cache memory, a second redundancy circuit coupled to the processor and the sideband communication line is coupled with the processor and the cache memory.

15. The processor according to claim 8, wherein a cache memory is coupled to the cache bus and wherein the redundancy logic includes a first redundancy circuit coupled to a memory control, a second redundancy circuit coupled to the processor and the sideband communication line is coupled with the processor the processor and the memory control.

16. A computer system comprising:

the processor to process data;

a system bus coupled to the processor;

a cache agent coupled to the system bus;

an L1 internal cache memory;

a redundancy circuit to generate a redundancy signal to indicate whether redundant portions of data occur in a string of data wherein the redundancy circuit includes a first redundancy circuit located in the L1 cache to generate a redundancy signal to indicate whether redundant data strings occur in a string of data located in the cache memory and comprises a second redundancy circuit located internal to the processor; and

a sideband communication line to transfer redundancy information.

17. The computer system according to claim 16, wherein the first redundancy circuit is coupled to the cache agent, the second redundancy circuit is coupled to the processor and the sideband communication line is coupled with the processor and the cache agent.

18. The computer system according to claim 16, wherein the redundancy circuit further comprises a list of predetermined portions of redundant data.

19. The computer system according to claim 16, further comprising a cache memory located external to the processor and wherein the first redundancy circuit is coupled to the cache memory, the second redundancy circuit is coupled to the processor and the sideband communication line is coupled with the processor and the cache memory.

20. The computer system according to claim 16, wherein the cache memory is coupled to the system bus and wherein the first redundancy circuit is coupled to the cache memory, the second redundancy circuit coupled to a memory control and the sideband communication line is coupled with the memory control and the cache memory.

21. The computer system according to claim 16, wherein the cache memory is coupled to the system bus and wherein the first redundancy circuit is coupled to the cache memory, the second redundancy circuit is coupled to the processor and the sideband communication line is coupled with the processor and the cache memory.

22. The computer system according to claim 16, wherein the cache memory is coupled to the system bus and wherein the first redundancy circuit is coupled to a memory control, the second redundancy circuit is coupled to the processor and the sideband communication line is coupled with the processor the processor and the memory control.

23. A computer system comprising:

the processor configured to process data;

a system bus coupled to the processor;

a cache agent coupled to the system bus;

a redundancy circuit configured to generate a redundancy signal to indicate whether redundant portions of data occur in a string of data;

cache memory located external to the processor wherein the redundancy circuit includes a first redundancy circuit coupled to the cache memory, a second redundancy circuit coupled to the processor; and

a sideband communication line to transfer redundancy information between the processor and the cache memory.

24. The computer system according to claim 23, wherein the first redundancy circuit is coupled to the cache agent, the second redundancy circuit is coupled to the processor and the sideband communication line is coupled with the processor and the cache agent.

25. The computer system according to claim 23, wherein the redundancy circuit further comprises a list of predetermined portions of redundant data.

26. The computer system according to claim 23, wherein the processor further comprises an L1 internal cache memory and wherein the first redundancy circuit is located in the L1 cache to generate a redundancy signal to indicate whether redundant data strings occur in a string of data located in the cache memory and the second redundancy circuit is located internal to the processor, and the sideband communication line is coupled with the processor and the L1 cache.

27. The computer system according to claim 23, wherein the cache memory is coupled to the system bus and wherein the first redundancy circuit is coupled to the cache memory, the second redundancy circuit is coupled to a memory control and the sideband communication line is coupled with the memory control and the cache memory.

28. The computer system according to claim 23, wherein the cache memory is coupled to the system bus and wherein the first redundancy circuit is coupled to the cache memory, the second redundancy circuit is coupled to the processor and the sideband communication line is coupled with the processor and the cache memory.

29. The computer system according to claim 23, wherein the cache memory is coupled to the system bus and wherein the redundancy circuit includes a first redundancy circuit coupled to the memory control, a second redundancy circuit coupled to the processor and a sideband communication line for communicating redundancy information between the processor the processor and the memory control.

30. A processor comprising:

an internal cache memory;

a cache bus for transferring portions of data between the internal cache memory and other locations;

redundancy logic for determining whether portions of data to be transferred are redundant; and

a sideband communication line for transferring redundancy information indicating whether redundant data occurs in a portion of data.

31. The processor of claim 30, wherein the redundancy logic includes a first redundancy circuit coupled to a cache agent, a second redundancy circuit coupled to the processor and the sideband communication line to transfer redundancy information between the processor and the cache agent.

32. The processor according to claim 30, wherein the redundancy logic further comprises a list of predetermined portions of redundant data.

33. The processor according to claim 30, wherein the processor further comprises an L1 internal cache memory and wherein the redundancy logic includes a first redundancy circuit located in the L1 cache to generate a redundancy signal to indicate whether redundant data strings occur in a string of data located in the cache memory and comprises a second redundancy circuit located internal to the processor, and the sideband communication line is coupled with the processor and the L1 cache.

34. The processor according to claim 30, further comprising a cache memory located external to the processor and wherein the redundancy logic includes a first redundancy circuit coupled to a cache memory, a second redundancy circuit coupled to the processor and the sideband communication line is coupled with the processor and the cache memory.

35. The processor according to claim 30, wherein a cache memory is coupled to the cache bus and wherein the redundancy logic includes a first redundancy circuit coupled to the cache memory, a second redundancy circuit coupled to a memory control and the sideband communication line is coupled with the memory control and the cache memory.

36. The processor according to claim 30, wherein a cache memory is coupled to the cache bus and wherein the redundancy logic includes a first redundancy circuit coupled to the cache memory, a second redundancy circuit coupled to the processor and the sideband communication line is coupled with the processor and the cache memory.

37. The processor according to claim 30, wherein a cache memory is coupled to the cache bus and wherein the redundancy logic includes a first redundancy circuit coupled to a memory control, a second redundancy circuit coupled to the processor and the sideband communication line is coupled with the processor the processor and the memory control.