Detection and exploitation of cache redundancies
First Claim
1. A computer system comprising:
- a processor to process data;
a system bus coupled to the processor;
a cache agent coupled to the system bus; and
a redundancy circuit including a first redundancy circuit coupled to the cache agent, a second redundancy circuit coupled to the processor and a sideband communication line to communicate redundancy information between the processor and the cache agent representing a redundancy signal to indicate whether redundant portions of data occur in, a string of data.
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Abstract
A method and apparatus are provided for reducing the number of cache line data transfers among components of a computer system, thus reducing the amount of traffic on a bus and increasing overall system performance. A sideband communication line is provided to transfer information from a source cache agent pertaining to redundant data strings occurring in a cache line to a destination cache agent. If redundant data strings occur in a cache line, the transfer of one or more portions of a cache line from the source to the destination can be canceled. Redundancy logic is provided to detect occurrences of redundant data strings located in a given cache line, generate and transfer redundancy bits when predetermined redundant data strings occur and decode redundancy bits at a destination cache agent to determine whether redundant data strings occur in subsequent cache lines to be transferred. The components benefiting from this invention can include a processor with its own on-chip L1 cache, a L2 or L3, an I/O controller or any other component that can perform cache functions. Alternative embodiments are provided of redundancy logic operating in parallel with data and instruction busses as well as redundancy logic operations occurring serially with the data and instruction busses.
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Citations
37 Claims
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1. A computer system comprising:
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a processor to process data;
a system bus coupled to the processor;
a cache agent coupled to the system bus; and
a redundancy circuit including a first redundancy circuit coupled to the cache agent, a second redundancy circuit coupled to the processor and a sideband communication line to communicate redundancy information between the processor and the cache agent representing a redundancy signal to indicate whether redundant portions of data occur in, a string of data. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A processor comprising:
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an internal cache memory;
a cache bus to transfer portions of data between the internal cache memory and other locations;
redundancy logic to determine whether portions of data to be transferred are redundant; and
a sideband communication line to transfer redundancy information indicating whether redundant data occurs in a portion of data. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15)
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16. A computer system comprising:
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the processor to process data;
a system bus coupled to the processor;
a cache agent coupled to the system bus;
an L1 internal cache memory;
a redundancy circuit to generate a redundancy signal to indicate whether redundant portions of data occur in a string of data wherein the redundancy circuit includes a first redundancy circuit located in the L1 cache to generate a redundancy signal to indicate whether redundant data strings occur in a string of data located in the cache memory and comprises a second redundancy circuit located internal to the processor; and
a sideband communication line to transfer redundancy information. - View Dependent Claims (17, 18, 19, 20, 21, 22)
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23. A computer system comprising:
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the processor configured to process data;
a system bus coupled to the processor;
a cache agent coupled to the system bus;
a redundancy circuit configured to generate a redundancy signal to indicate whether redundant portions of data occur in a string of data;
cache memory located external to the processor wherein the redundancy circuit includes a first redundancy circuit coupled to the cache memory, a second redundancy circuit coupled to the processor; and
a sideband communication line to transfer redundancy information between the processor and the cache memory. - View Dependent Claims (24, 25, 26, 27, 28, 29)
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30. A processor comprising:
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an internal cache memory;
a cache bus for transferring portions of data between the internal cache memory and other locations;
redundancy logic for determining whether portions of data to be transferred are redundant; and
a sideband communication line for transferring redundancy information indicating whether redundant data occurs in a portion of data. - View Dependent Claims (31, 32, 33, 34, 35, 36, 37)
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Specification