Implantable medical stimulation device having reconfigurable memory

• US 6,535,765 B1
• Filed: 06/08/2001
• Issued: 03/18/2003
• Est. Priority Date: 06/08/2001
• Status: Active Grant

• Current Assignee: Pacesetter Incorporated (Abbott Laboratories Incorporated)
• Original Assignee: Pacesetter Incorporated (Abbott Laboratories Incorporated)
• Inventors: Badelt, Steven W., Amely-Velez, Jorge N., Darbidian, Dro
• Primary Examiner(s): Schaetzle, Kennedy
• Application Number:
  US09/877,623
• Time in Patent Office: 648 Days
• Field of Search: 607/4, 607/5, 607/59, 607/2, 607/9, 607/27, 607/30, 711/1, 711/6, 711/147, 711/170, 711/173
• US Class Current: 607/59
• CPC Class Codes: A61N 1/37211 Means for communicating with stimulators
• CPC Class Codes: A61N 1/37264 Changing the program; Upgrading firmware
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70

Abstract

The implantable medical device is provided with typically equal portions of both random access memory (RAM) and read only memory (ROM) and a virtual memory space is defined equal to the amount of memory in one of the memory devices. In a specific example, the RAM and ROM provide 256K of memory each, with the virtual memory space also set to 256K. A zone control register is provided which specifies, for each of a set of predetermined zones within the virtual memory space, whether memory access commands are to be routed to RAM or ROM. Control bits within the zone control register may be reset to permit portions of memory to be remapped from one memory device to the other. By providing RAM and ROM each typically equal in size to the virtual memory space, software for use in the device may be tested and debugged using RAM then transferred to ROM for use in production devices. By providing dual RAM and ROM, software upgrades or software bug fixes are easily performed merely by downloading new software into RAM, then resetting the zone control register to point to RAM, rather than ROM. Additionally, when necessary, the overall virtual memory space may be expanded to encompass both the RAM and ROM thereby permitting access to greater quantities of memory.

Claims

1. In an implantable medical device having various computing components accessing a virtual memory space corresponding to a predetermined amount of memory, a memory system comprising:

dynamic memory means for dynamically storing data, the dynamic memory means corresponding in size to at least the predetermined amount of memory;

permanent memory means for statically storing data, the permanent memory means also corresponding in size to at least the predetermined amount of memory; and

memory controller means for dynamically mapping selected portions of the virtual memory space to either the dynamic memory means or the permanent memory means, such that the entire virtual memory space can be mapped, if needed, to either just the dynamic memory means or to just the static memory means.

2. The memory system of claim 1 wherein the dynamic memory means is a RAM, flash memory or EEPROM.

3. The memory system of claim 1 wherein the permanent memory means is a ROM.

4. The memory system of claim 1 wherein the memory controller means is preprogrammed to always map certain predetermined portions of the virtual memory to the dynamic memory means.

5. The memory system of claim 4 wherein the predetermined portions of the virtual memory space include portions requiring dynamic access.

6. The memory system of claim 5 wherein the portions requiring dynamic access include one or more of portions dedicated to storing page zero information, stack information, mailbox information, patient data and stored internal electrocardiogram (IEGM) data.

7. The memory system of claim 1 wherein the memory controller includes a means for specifying, for each of a predetermined number of zones of the virtual memory, whether the memory is mapped to the dynamic memory means or the permanent memory means.

8. The memory system of claim 7 wherein the means for specifying whether the memory is mapped to dynamic memory means or permanent memory means is a zone control register.

9. The memory system of claim 8 wherein the zone control register is a binary register having one bit per predetermined memory zone, the bit set to a first binary value to indicate the dynamic memory means and to a second binary value to indicate the permanent memory means.

10. The memory system of claim 1 wherein the memory controller means receives an indication of a corrupted portion of memory within the dynamic memory means or the permanent memory means and re-maps the portion of the virtual memory space previously mapped to the corrupted portion of memory to a corresponding portion of memory in the other memory means.

11. The memory system of claim 1 wherein the memory controller means receives updated data for replacing a portion of data of the permanent memory means, stores the updated data within the dynamic memory means, and re-maps the virtual memory space to access the updated data of the dynamic memory means.

12. The memory system of claim 11 wherein the updated data includes software.

13. The memory system of claim 1 wherein the memory controller means receives an indication of data of the permanent memory means to be accessed instead of data of the dynamic memory means and re-maps the virtual memory space to access the data of the permanent memory means instead of data of the dynamic memory means.

14. The memory system of claim 1 wherein virtual memory space exceeds the predetermined amount of memory and wherein the memory controller means maps memory addresses lying within the virtual memory space but outside of the predetermined amount of memory to the portions of the dynamic memory means not mapped by the memory controller means.

15. The memory system of claim 1 for use within an implantable medical device selected from a group including a pacemaker and an implantable cardioverter defibrillator (ICD).

16. The memory system of claim 1 for use within an implantable medical device having various computing components accessing two or more virtual memory spaces.

17. In an implantable medical device, a memory system comprising:

a controller accessing a virtual memory space corresponding to a predetermined amount of memory;

a dynamic memory unit corresponding in size to at least the predetermined amount of memory;

a permanent memory unit also corresponding in size to at least the predetermined amount of memory; and

memory controller dynamically mapping selected portions of the virtual memory space to either the dynamic memory unit or the permanent memory unit, such that the entire virtual memory space can be mapped, if needed, to either just the dynamic memory unit or to just the static memory unit.

18. The memory system of claim 17 wherein the dynamic memory unit is a RAM, flash memory or EEPROM.

19. The memory system of claim 17 wherein the permanent memory unit is a ROM.

20. The memory system of claim 17 wherein the memory controller is preprogrammed to always map certain predetermined portions of the virtual memory to dynamic memory unit.

21. The memory system of claim 20 wherein the predetermined portions of the virtual memory space include portions requiring dynamic access.

22. The memory system of claim 21 wherein the portions requiring dynamic access include one or more of portions dedicated to storing page zero information, stack information, mailbox information, patient data and stored internal electrocardiogram (IEGM) data.

23. The memory system of claim 17 wherein the memory controller specifies, for each of a predetermined number of zones of the virtual memory, whether the memory is mapped to the dynamic memory unit or the permanent memory unit.

24. The memory system of claim 23 wherein the memory controller includes a zone control register.

25. The memory system of claim 24 wherein the zone control register is a binary register having one bit per predetermined memory zone, the bit set to a first binary value to indicate the dynamic memory unit and to a second binary value to indicate the permanent memory unit.

26. The memory system of claim 17 wherein the memory controller receives an indication of a corrupted portion of memory within the dynamic memory unit or the permanent memory unit and re-maps the portion of the virtual memory space previously mapped to the corrupted portion of memory to a corresponding portion of memory in the other memory unit.

27. The memory system of claim 17 wherein the memory controller receives updated data for replacing a portion of data of the permanent memory unit, stores the updated data within the dynamic memory unit, and re-maps the virtual memory space to access the updated data of the dynamic memory unit.

28. The memory system of claim 27 wherein the updated data includes software.

29. The memory system of claim 17 wherein the memory controller receives an indication of data of the permanent memory unit to be accessed instead of data of the dynamic memory unit and re-maps the virtual memory space to access the data of the permanent memory unit instead of data of the dynamic memory unit.

30. The memory system of claim 17 wherein virtual memory space exceeds the predetermined amount of memory and wherein the memory controller maps memory addresses lying within the virtual memory space but outside of the predetermined amount of memory to the portions of the dynamic memory unit not mapped by the memory controller.

31. The memory system of claim 17 for use within an implantable medical device selected from a group including a pacemaker and an implantable cardioverter defibrillator (ICD).

32. The memory system of claim 17 for use within an implantable medical device having various computing components accessing two or more virtual memory spaces.

33. In an implantable medical device having a microcontroller capable of accessing a virtual memory space, a memory system including a dynamic memory unit and a static memory unit, with each memory unit having sufficient memory to accommodate the entire virtual memory space, and a memory controller for dynamically mapping selected portions of the virtual memory space to either the dynamic memory unit or the static memory unit, a method for controlling memory access comprising the steps of:

storing control software in the static memory unit and configuring the memory controller to map portions of the virtual memory space corresponding to control software to the static memory unit;

storing data in the dynamic memory unit and configuring the memory controller to map portions of the virtual memory space corresponding to data to the dynamic memory unit;

receiving a memory access command from the microcontroller specifying a virtual memory address;

determining, using the memory controller, whether the virtual memory address is currently mapped to the dynamic memory unit or the static memory unit; and

forwarding the memory access command to the respective memory unit for accessing memory therein.

34. The method of claim 33 further comprising the steps of:

storing modified control software in the dynamic memory unit; and

configuring the memory controller to re-map portions of the virtual memory space corresponding to the updated control software to the dynamic memory unit instead of to the static memory unit such that subsequent memory access commands to virtual memory addresses corresponding to the modified control software are automatically directed to the dynamic memory unit rather than to the static memory unit.

35. The method of claim 33 further comprising the steps of:

configuring the microcontroller to access a larger virtual memory space than accommodated by either the dynamic memory unit or the static memory unit alone; and

configuring the memory controller to map a first portion of the larger virtual memory space to the static memory unit and a second portion of the larger virtual memory space to the dynamic memory unit such that subsequent memory access commands to the first portion of the virtual memory space are automatically directed to the static memory unit and subsequent memory access commands to the second portion of the virtual memory space are automatically directed to the dynamic memory unit.