Low-latency circuit for synchronizing data transfers between clock domains derived from a common clock

• US 6,535,946 B1
• Filed: 01/04/2000
• Issued: 03/18/2003
• Est. Priority Date: 01/04/2000
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Bryant, Christopher D., Edenfield, Robin W.
• Primary Examiner(s): THAI, XUAN MARIAN
• Application Number:
  US09/477,321
• Time in Patent Office: 1,169 Days
• Field of Search: 710/305 713/400 375/354 327/141,144,145,146 325/147
• US Class Current: 710/305
• CPC Class Codes: G06F 5/06 for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor G06F7/78 takes precedence
• CPC Class Codes: H04L 7/0045 Correction by a latch cascade
• CPC Class Codes: H04L 7/02 Speed or phase control by the received code signals, the signals containing no special synchronisation information H04L7/0075 takes precedence
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

There is disclosed, for use in an x86-compatible processor, an interface circuit for synchronizing the transfer of signals between different clock domains derived from a common core clock, where the phase and frequency relationships between the different domain clocks are known. The interface circuit comprises 1) a first latch having a data input for receiving a data signal from the first clock domain, a clock input for receiving the first clock signal, and an output; 2) a second latch having a data input coupled to the first latch output, an enable input for receiving a gating signal, a clock input for receiving the first clock signal, and an output; 3) a third latch having a data input for receiving the data signal, an enable input for receiving a gating signal, a clock input for receiving the first clock signal, and an output; and 4) a multiplexer having a first data input coupled to the second latch output, a second data input coupled to the third latch output, and a selector input for selecting one of the first data input and the second data input for transfer to an output of the multiplexer.

Claims

1. An interface circuit for synchronizing the transfer of data through an output port from a first clock domain driven by a first clock signal to a second clock domain driven by a second clock signal, the interface circuit comprising:

a first latch having a data input for receiving a data signal from said first clock domain, an enable input for receiving said first clock signal, a clock input for receiving said first clock signal; and

an output;

a second latch having a data input coupled to said first latch output, a clock input for receiving a gating signal, a clock input for receiving said first clock signal, and an output;

a third latch having a data input for receiving said data signal, an enable input for receiving a phase select signal, a clock input for receiving said first clock signal, and an output; and

a multiplexer having a first data input coupled to said second latch output, a second data input coupled to said third latch output, and a selector input for selecting one of said first data input and said second data input for transfer to an output of said multiplexer.

2. The interface circuit set forth in claim 1 wherein said second clock signal and said first clock signal are derived from a common core clock.

3. The interface circuit set forth in claim 2 wherein a frequency of said second clock signal and a frequency of said first clock signal are in a ratio of N:

1 where N is an integer.

4. The interface circuit set forth in claim 3 wherein a selection signal applied to the selector input selects said first data input of said multiplexer when a rising edge of said first clock signal is approximately in phase with a rising edge of said second clock signal.

5. The interface circuit set forth in claim 2 wherein a frequency of said second clock signal and a frequency of said first clock signal are in a ratio of (N+2):

1 where N is an integer.

6. The interface circuit set forth in claim 5 wherein a selection signal applied to the selector input selects said first data input of said multiplexer during one clock cycle of said second clock signal.

7. An interface circuit for synchronizing the transfer of data from an output of a state machine in a first clock domain driven by a first clock signal to a second clock domain driven by a second clock signal, the interface circuit comprising:

a first latch having a data input for receiving said state machine output, an enable input that is set to an enabled value, and an output; and

a second latch having a data input coupled to said first latch output, an enable input for receiving a gating signal, a clock input for receiving said first clock signal, and an output coupled to an input of said state machine.

8. The interface circuit set forth in claim 7 wherein said second clock signal and said first clock signal are derived from a common core clock.

9. The interface circuit set forth in claim 8 wherein a frequency of said second clock signal and a frequency of said first clock signal are in a ratio of N:

1 where N is an integer.

10. The interface circuit set forth in claim 8 wherein a frequency of said second clock signal and a frequency of said first clock signal are in a ratio of (N+2):

1 where N is an integer.

11. A computer system comprising:

a pipelined, x86-compatible processor having dual integer and dual floating point execution units, separate load/store and branch units, an L1 instruction cache and an L1 data cache;

system memory for storing data or instructions;

a core clock; and

an interface circuit for synchronizing the transfer of data through an output port from a first clock domain driven by a first clock signal to a second clock domain driven by a second clock signal, the interface circuit comprising;

a first latch having a data input for receiving a data signal from said first clock domain, a clock input for receiving said first clock signal, an enable input that is set to an enabled value and an output;

a second latch having a data input coupled to said first latch output, an enable input for receiving a gating signal, a clock input for receiving said first clock signal, and an output;

a third latch having a data input for receiving said data signal, a enable input for receiving a phase select signal, a clock input for receiving said first clock signal, and an output; and

a multiplexer having a first data input coupled to said second latch output, a second data input coupled to said third latch output, and a selector input for selecting one of said first data input and said second data input for transfer to an output of said multiplexer.

12. The computer system set forth in claim 11 wherein said second clock signal and said first clock signal are derived from said core clock.

13. The computer system set forth in claim 12 wherein a frequency of said second clock signal and a frequency of said first clock signal are in a ratio of N:

1 where N is an integer.

14. The computer system set forth in claim 13 wherein a selection signal applied to the selector input selects said first data input of said multiplexer when a rising edge of said first clock signal is approximately in phase with a rising edge of said second clock signal.

15. The computer system set forth in claim 12 wherein a frequency of said second clock signal and a frequency of said first clock signal are in a ratio of (N+2):

1 where N is an integer.

16. The computer system set forth in claim 15 wherein a selection signal applied to the selector input selects said first data input of said multiplexer during one clock cycle of said second clock signal.

17. A computer system comprising:

a pipelined, x86-compatible processor having dual integer and dual floating point execution units, separate load/store and branch units, an L1 instruction cache and an L1 data cache;

system memory for storing data or instructions;

a core clock; and

an interface circuit for synchronizing the transfer of data from an output of a state machine in a first clock domain driven by a first clock signal to a second clock domain driven by a second clock signal, the interface circuit comprising;

a first latch having a data input for receiving said state machine output, a clock input for receiving said first clock signal, an enable input set to an enabled value, and an output; and

a second latch having a data input coupled to said first latch output, an enable input for receiving a gating signal, a clock input for receiving said first clock signal, and an output coupled to an input of said state machine.

18. The computer system set forth in claim 17 wherein said second clock signal and said first clock signal are derived from a common core clock.

19. The computer system set forth in claim 18 wherein a frequency of said second clock signal and a frequency of said first clock signal are in a ratio of N:

1 where N is an integer.

20. The computer system set forth in claim 18 wherein a frequency of said second clock signal and a frequency of said first clock signal are in a ratio of (N+2):

1 where N is an integer.