Semiconductor memory device having a refresh operation

• US 6,535,950 B1
• Filed: 03/29/2000
• Issued: 03/18/2003
• Est. Priority Date: 06/10/1999
• Status: Expired due to Term

• Current Assignee: Socionext Inc.
• Original Assignee: Fujitsu Limited
• Inventors: Fujioka, Shinya, Sato, Kotoku, Suzuki, Takaaki, Ikeda, Hitoshi, Matsuzaki, Yasurou, Taguchi, Masao, Funyu, Akihiro, Satoh, Kimiaki
• Primary Examiner(s): Robertson, David L.
• Application Number:
  US09/536,988
• Time in Patent Office: 1,084 Days
• Field of Search: 711/106, 365/230, 365/222
• US Class Current: 711/106
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40615 Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
• CPC Class Codes: G11C 11/40618 Refresh operations over multiple banks or interleaving
• CPC Class Codes: G11C 11/4072 Circuits for initialization, powering up or down, clearing memory or presetting
• CPC Class Codes: G11C 7/1042 using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
• CPC Class Codes: G11C 7/1063 Control signal output circuits, e.g. status or busy flags, feedback command signals
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory

Abstract

A semiconductor memory device, such as a DRAM, which needs to be refreshed for retaining data, is provided with a storing portion for storing data therein, and a busy signal outputting portion outputting a busy signal during the refresh operation.

Claims

1. A semiconductor memory device, comprising:

memory blocks, each comprising memory cells; and

word lines provided for selecting said memory cells,

wherein, while the memory cells selected by the word line are being refreshed, said device accepts a command sent for the memory block including said word line, interrupts a refresh operation of said memory cells selected by said word line, saves data of said memory cells which are being refreshed into a register, then executes the command, and, then, restarts the refresh operation of said memory cells selected by said word line.

2. A semiconductor memory device, comprising:

memory blocks, each comprising memory cells; and

word lines provided for selecting said memory cells,

a register in which the data of the memory cells which are being refreshed is saved; and

a transfer gate which causes data to be transferred to said register,

wherein, while the memory cells selected by the word line are being refreshed, said device accepts a command sent for the memory block including said word line, interrupts a refresh operation of said memory cells selected by said word line, executes the command, and, then, restarts the refresh operation of said memory cells selected by said word line and;

wherein execution of the command is performed after the data of said memory cells which is being refreshed is saved in said register via said transfer gate, and, when the refresh operation is restarted, the data is returned from said register.

3. The semiconductor memory device as claimed in claim 2, wherein said device accepts a second command while performing the restarted refresh operation, interrupts the restarted refresh operation, performs the second command, and restarts the refresh operation.

4. The semiconductor memory device as claimed in claim 2, said transfer gate causes the data on bit lines, which data is being amplified by a sense amplifier, to be transferred to said register.

5. The semiconductor memory device as claimed in claim 2, said transfer gate causes the data on bit lines, which data is not being amplified by a sense amplifier, to be transferred to said register.

6. The semiconductor memory device as claimed in claim 2, further comprising a comparator which compares the address for which the refresh operation is being performed and the row address for performing the command, wherein the refresh operation is interrupted and the command is performed when the address for which the refresh operation is being performed is not coincident with the row address for performing the command, but the refresh operation is completed, pre-charging of bit lines are not performed and the command is executed when the address for which the refresh operation is being performed is coincident with the row address for performing the command.

7. The semiconductor memory device as claimed in claim 6, wherein, when the refresh operation is interrupted as a result of the address for which the refresh operation is being performed being not coincident with the row address for performing the command, a time period for which pre-charging is performed subsequent to the interruption of the refresh operation is adjusted depending on the time period from the commencement of the refresh operation to the interruption of the refresh operation.