Communication error reporting mechanism in a multiprocessing computer system
First Claim
1. A subsystem for a multiprocessing computer system, said subsystem comprising:
- a first processor coupled to a local bus, said first processor including a first error status register;
a second processor coupled to said local bus, said second processor including a second error status register;
a system interface coupled to said local bus, wherein said system interface is configured to receive transactions directed to one or more remote nodes which are initiated by said first and second processors, wherein said system interface is configured to provide a first error code to be stored within said first error status register in response to a first error being generated as a result of a first transaction initiated by said first processor, and wherein said system interface is configured to provide a second error code to be stored within said second error status register in response to a second error being generated as a result of a second transaction initiated by said second processor.
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Accused Products
Abstract
A multiprocessing computer system includes a plurality of processing nodes, each having one or more processors, a memory, and a system interface. The plurality of processing nodes may be interconnected through a global interconnect network which supports cluster communications. The system interface of an initiating node may launch a request to a remote node'"'"'s memory or I/O. The computer system implements an error communication reporting mechanism wherein errors associated with remote transactions may be reported back to a particular processor which initiated the transaction. Each processor includes an error status register that is large enough to hold a transaction error code. The protocol associated with a local bus of each node (i.e., a bus interconnecting the processors of a node to the node'"'"'s system interface) includes acknowledgement messages for transactions when they have completed. In the event a transaction which is transmitted by a system interface upon the global interconnect network on behalf of a particular processor incurs an error, the system interface sets an error flag in the acknowledgement message and provides an associated error code. If the acknowledgement message denotes an error, the error code is written into the processor'"'"'s error status register for later retrieval by software. In various embodiments, a system interface may acknowledge a transaction to a given processor early (even if that transaction has not completed globally) if a subsequent transaction from the same processor is pending in the interface.
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Citations
24 Claims
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1. A subsystem for a multiprocessing computer system, said subsystem comprising:
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a first processor coupled to a local bus, said first processor including a first error status register;
a second processor coupled to said local bus, said second processor including a second error status register;
a system interface coupled to said local bus, wherein said system interface is configured to receive transactions directed to one or more remote nodes which are initiated by said first and second processors, wherein said system interface is configured to provide a first error code to be stored within said first error status register in response to a first error being generated as a result of a first transaction initiated by said first processor, and wherein said system interface is configured to provide a second error code to be stored within said second error status register in response to a second error being generated as a result of a second transaction initiated by said second processor. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A multiprocessing computer system comprising a plurality of processing nodes and a global interconnect network interconnecting said plurality of processing nodes, wherein a first node includes:
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a plurality of processors;
a memory coupled to said plurality of processors through a local bus; and
a system interface for receiving local transactions initiated by said plurality of processors on said local bus which are destined to remote nodes;
wherein each of said plurality of processors includes an error status register configured to store information regarding an error associated with a global transaction conveyed upon said global interconnect network by said system interface that corresponds to one of said local transactions;
wherein said system interface is configured to generate an acknowledgement message in response to a given transaction. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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22. A processor for use in a first node of a multiprocessing computer system that is interconnected with a plurality of additional processing nodes through a global interconnect network, wherein said first node includes a system interface for receiving transactions from said processor which are destined to at least one of said additional processing nodes, said processor comprising:
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a processor core configured to initiate said transactions;
an error status register coupled to said processor core and configured to store error information regarding an error associated with a global transaction conveyed upon said global interconnect network by said system interface that correponds to a given transaction initiated by said processor core;
a bus interface configured to receive said error information from said system interface; and
software code executable to periodically poll said error status register to detect an error associated with said global transaction. - View Dependent Claims (23, 24)
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Specification