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High-speed failure capture apparatus and method for automatic test equipment

  • US 6,536,005 B1
  • Filed: 10/26/1999
  • Issued: 03/18/2003
  • Est. Priority Date: 10/26/1999
  • Status: Expired due to Term
First Claim
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1. A failure capture circuit for use in a failure processing circuit to identify failure location information from a memory-under-test (MUT), said MUT having a predetermined storage capacity comprising a plurality of memory cells, said failure capture circuit including:

  • failure detection circuitry comprising a plurality of channels and adapted for coupling to said MUT and operative to apply test signals to said MUT and process output signals from said MUT into failure information;

    a failure memory circuit including slice circuitry including I/O selection logic and routing circuitry disposed at the output of said I/O selection logic;

    memory comprising a plurality of memory banks, said banks having substantially similar address rows and columns and configured to receive said failure signals in a random mode, said banks having respective burst mode inputs and outputs; and

    reconcile circuitry coupled to said respective burst mode outputs and having a reconcile path to said bank inputs and operative to, after said banks have captured a predetermined amount of data, ensure that each of said substantially similar addresses of said banks contains the same data; and

    a high-speed link coupling said failure memory circuit to said failure detection circuitry, wherein said high-speed link comprises a serial data link.

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