Standard block architecture for integrated circuit design

• US 6,536,028 B1
• Filed: 03/14/2000
• Issued: 03/18/2003
• Est. Priority Date: 03/14/2000
• Status: Expired due to Fees

• Current Assignee: AmmoCore Technology, Inc.
• Original Assignee: AmmoCore Technology, Inc.
• Inventors: Avidan, Jacob, Fotakis, Dimitris, Katsioulas, Athanassios, Chow, Stan
• Primary Examiner(s): Siek, Vuthe
• Assistant Examiner(s): LIN, SUN J
• Application Number:
  US09/525,184
• Time in Patent Office: 1,099 Days
• Field of Search: 716/1-18
• US Class Current: 716/125
• CPC Class Codes: G06F 2115/08 Intellectual property [IP] blocks or IP cores
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347

Abstract

A STANDARD BLOCK architecture for integrated circuit (IC) design. The STANDARD BLOCK architecture provides a new level of abstraction with a granularity and regularity that is most appropriate for the physical implementation of complex, large scale deep-submicron IC designs. To this end, the STANDARD BLOCK architecture combines the advantages of standard-cell-based and functional-block-based architectures. The STANDARD BLOCK architecture includes a STANDARD BLOCK form that is physically constrained having one fixed or quantized dimension and one variable dimension that ranges between predefined limits. The STANDARD BLOCK granularity is larger than the standard cell granularity such that each STANDARD BLOCK includes a plurality of standard cells. In the STANDARD BLOCK architecture, each STANDARD BLOCK has flexible physical design properties. In this design style, the STANDARD BLOCKs are provided as general physical abstractions such that each STANDARD BLOCK is akin to a black box model with the majority of its internal design aspects invisible to the top-level assembly tool while selected design aspects remain visible. The global design aspects of each STANDARD BLOCK include its fundamental architectural and structural characteristics, including its physically constrained form, and its fundamental power, timing, clock and signal integrity properties. With the STANDARD BLOCK architecture, quantization of the STANDARD BLOCKs'"'"' form dimensions relative to IC dimensions can be substantially constant and scalable with increased IC complexity. Thus, STANDARD BLOCK architecture can be applied to any IC designs as well as any intellectual property (IP) designs.

Claims

1. A standard block architecture for an integrated circuit, said architecture comprising:

a standard block form having a quantized dimension and a variable dimension, said quantized dimension being a selected multiple of a standard cell height of a standard cell, said variable dimension being constrained between a minimum dimension and a maximum dimension; and

a standard block granularity and abstraction level, said granularity and said level of abstraction being larger and higher, respectively, than a corresponding granularity and level of abstraction of the standard cell.

2. A standard block architecture as set forth in claim 1 wherein said standard block form is substantially rectangular.

3. A standard block architecture as set forth in claim 2 wherein said quantized dimension is a height of said standard block form and said variable dimension is a length of said standard block form.

4. A standard block architecture as set forth in claim 2 wherein said quantized dimension is a length of said standard block form and said variable dimension is a height of said standard block form.

5. A standard block architecture as set forth in claim 1 further comprising a plurality of standard cells disposed within said standard block form.

6. A standard block architecture as set forth in claim 5 wherein said standard cells are arranged in a row based array configuration aligned with said variable dimension.

7. A standard block architecture as set forth in claim 5 said standard cells are arranged in a column based array configuration aligned with said variable dimension.

8. A standard block architecture as set forth in claim 5 wherein each of said standard cells has a constant dimension, said quantized dimension being a selected integer multiple of said constant dimension.

9. A standard block architecture as set forth in claim 8 wherein said quantized dimension is a height of said standard block form, said standard cells being arranged in a row based array configuration with said constant dimension being aligned with said quantized dimension.

10. A standard block architecture as set forth in claim 8 wherein said quantized dimension is a length of said standard block form, said standard cells being arranged in a column based array configuration with said constant dimension being aligned with said quantized dimension.

11. A standard block architecture as set forth in claim 5 wherein said standard cells have pins, related ones of said pins being grouped to define a virtual pin.

12. A standard block architecture as set forth in claim 5 further comprising levels of metal layers wherein interconnects to said standard cells within the standard block are completed using lower levels of said metal layers.

13. A standard block architecture as set forth in claim 5 further comprising levels of metal layers wherein interconnections to said standard cells external to the standard block are completed using higher levels of said metal layers.

14. A standard block architecture as set forth in claim 5 further comprising levels of metal layers wherein said standard cells have power and ground connections, related ones of said power and ground connections are made using lower levels of said metal layers.

15. A standard block architecture as set forth in claim 5 wherein unutilized spaces in said standard block form are adaptable to include selectively clock buffers and inserted buffers, and routing tracks through said standard block.

16. A standard block architecture as set forth in claim 5 wherein unutilized spaces in said standard block form are adaptable to be designated as routing tracks through said standard block.

17. A standard block architecture as set forth in claim 5 wherein said standard cells contained within said standard block form are dissociated from a logical hierarchy of a gate level netlist.