Forming semiconductor structures including activated acceptors in buried p-type III-V layers

• US 6,537,838 B2
• Filed: 06/11/2001
• Issued: 03/25/2003
• Est. Priority Date: 06/11/2001
• Status: Expired due to Fees

• Current Assignee: Lumileds LLC (Apollo Global Management, Inc.)
• Original Assignee: Limileds Lighting US LLC
• Inventors: Stockman, Stephen A.
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Le, Dung Anh
• Application Number:
  US09/879,549
• Publication Number:
  US 20020187568A1
• Time in Patent Office: 652 Days
• Field of Search: 438/45-47, 438/507-509, 257/96, 257/101-103, 257/201, 257/613, 257/615, 257/609
• US Class Current: 438/22
• CPC Class Codes: H01L 21/3245 of AIIIBV compounds
• CPC Class Codes: H01L 33/0095 Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
• CPC Class Codes: H01L 33/305 characterised by the doping materials

Abstract

To allow hydrogen to out-diffuse from a buried Group III-nitride compound semiconductor p-type layer, the wafer is etched to form trenches in the p-type layer to expose sides of the p-type layer. After the etch, the wafer is then annealed. The duration and temperature of the anneal depend upon the spacing of the exposed sides of the p-type layer and the thickness of the p-type layer. The hydrogen diffuses easily through the p-type layer and out the sides exposed by the trenches. The result is a buried p-type layer that is more highly conductive than had the trenches not been formed prior to the anneal. In another embodiment, a surface of an acceptor-doped Group III-V p-type layer is covered with an overlying n-type layer. A portion of the n-type layer is etched to expose the surface of the p-type layer. An anneal is then carried out to out-diffuse hydrogen from the exposed surface of the p-type layer to increase the conductivity of the p-type layer.

Claims

1. A method for forming a semiconductor structure comprising:

forming a Group III-V compound semiconductor layer doped with acceptors to form an acceptor-doped layer, a majority of acceptors being passivated by hydrogen in said acceptor-doped layer;

forming a Group III-V n-type layer overlying said acceptor-doped layer;

etching said n-type layer to expose a portion of said acceptor-doped layer; and

annealing said acceptor-doped layer to out-diffuse hydrogen at least through the exposed portion of said acceptor-doped layer to activate said acceptors to increase a hole density in said acceptor-doped layer and decrease a resistivity of said acceptor-doped layer.

2. The method of claim 1 wherein said etching comprises etching trenches in said acceptor-doped layer to expose sides of said acceptor-doped layer and said annealing comprises annealing said acceptor-doped layer to out-diffuse hydrogen through said sides of said acceptor-doped layer exposed by said trenches.

3. The method of claim 1 further comprising forming a second n-type layer underlying said acceptor-doped layer.

4. The method of claim 2 wherein said forming trenches comprises forming trenches between approximately 1 micron to 1000 microns apart.

5. The method of claim 1 wherein said forming said acceptor-doped layer comprises forming an acceptor-doped layer between approximately 500 Angstroms and 5 microns thick.

6. The method of claim 1 wherein said annealing out-diffuses substantially all of said hydrogen.

7. The method of claim 1 wherein said acceptors comprise magnesium.

8. The method of claim 1 wherein said semiconductor structure forms a light emitting device.

9. The method of claim 8 further comprising forming a second n-type layer underlying said acceptor-doped layer to form a tunnel junction light emitting device.

10. The method of claim 1 further comprising forming a second n-type layer underlying said acceptor-doped layer to form a heterojunction bipolar transistor.

11. The method of claim 1 wherein said annealing is carried out at a temperature less than approximately 850°

C.

12. The method of claim 1 wherein said annealing is carried out at a temperature between approximately 400°

C.-600°

C.

13. The method of claim 1 wherein said acceptor-doped layer comprises a plurality of layers.

14. The method of claim 1 wherein said etching comprises etching said second layer to expose a surface of said acceptor-doped layer.

15. The method of claim 1, wherein said Group III-V n-type layer comprises a plurality of layers.