SOI transistor with body contact and method of forming same
First Claim
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1. A method for fabricating an SOI field effect transistor having a source and a drain separated by a gate disposed along a gate axis, a body region disposed below said gate and a body contact, in which said body contact is isolated from said gate, said source and said drain by a body isolation trench located in a body isolation trench region of said transistor, characterized by the steps of:
- a) preparing an SOI substrate including a device layer, having a device layer thickness, disposed above and in contact with a buried insulating layer having a buried layer thickness;
b) depositing a trench pattern layer on the surface of said device layer;
c) etching a shallow trench isolation pattern covering shallow isolation trenches and said body isolation trench region into said pattern layer, thereby exposing said device layer in said shallow trench isolation pattern;
d) depositing a blocking layer above said body isolation trench region;
e) etching said device layer in said shallow trench isolation pattern down to a first depth less than said device layer thickness by an amount substantially equal to a body isolation depth of said body isolation trench;
f) removing said blocking layer and etching said device layer down to said buried layer in said shallow isolation trenches, whereby, simultaneously with the etching of said shallow isolation trenches, said body isolation region is etched to said body isolation depth less than said device layer thickness, so that a conductive path extends in said device layer along said gate axis from said body region to said body contact;
g) filling the trenches formed in said etching step with an insulating material and planarizing the surface of the resulting structure; and
h) completing said transistor.
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Abstract
An SOI field effect transistor is provided comprising a body contact that is isolated by a shallow trench that is formed into the body portion of the transistor, thereby eliminating any increase in gate capacitance or delay. A method of forming such a transistor is provided that does not require any additional process steps.
86 Citations
7 Claims
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1. A method for fabricating an SOI field effect transistor having a source and a drain separated by a gate disposed along a gate axis, a body region disposed below said gate and a body contact, in which said body contact is isolated from said gate, said source and said drain by a body isolation trench located in a body isolation trench region of said transistor, characterized by the steps of:
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a) preparing an SOI substrate including a device layer, having a device layer thickness, disposed above and in contact with a buried insulating layer having a buried layer thickness;
b) depositing a trench pattern layer on the surface of said device layer;
c) etching a shallow trench isolation pattern covering shallow isolation trenches and said body isolation trench region into said pattern layer, thereby exposing said device layer in said shallow trench isolation pattern;
d) depositing a blocking layer above said body isolation trench region;
e) etching said device layer in said shallow trench isolation pattern down to a first depth less than said device layer thickness by an amount substantially equal to a body isolation depth of said body isolation trench;
f) removing said blocking layer and etching said device layer down to said buried layer in said shallow isolation trenches, whereby, simultaneously with the etching of said shallow isolation trenches, said body isolation region is etched to said body isolation depth less than said device layer thickness, so that a conductive path extends in said device layer along said gate axis from said body region to said body contact;
g) filling the trenches formed in said etching step with an insulating material and planarizing the surface of the resulting structure; and
h) completing said transistor. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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Current AssigneeInternational Business Machines Corporation
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Original AssigneeInternational Business Machines Corporation
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InventorsKroell, Karl-Eugen, Pille, Juergen, Schettler, Helmut
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Primary Examiner(s)Lebentritt, Michael S.
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Assistant Examiner(s)Luu, Pho M.
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Application NumberUS09/382,108Time in Patent Office1,309 DaysField of Search438/149, 438/299, 357/23.5, 257/301, 257/347, 257/310US Class Current438/149CPC Class CodesH01L 29/66772 Monocristalline silicon tra...H01L 29/7841 with floating body, e.g. pr...H01L 29/78615 with a body contact
