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Circuit and method for an open bit line memory cell with a vertical transistor and trench plate trench capacitor

  • US 6,537,871 B2
  • Filed: 12/20/2000
  • Issued: 03/25/2003
  • Est. Priority Date: 10/06/1997
  • Status: Expired due to Term
First Claim
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1. A method of fabricating an array of memory cells, comprising:

  • providing a substrate;

    forming a plurality of access transistors, each access transistor formed in a pillar of semiconductor material extending outwardly from the substrate and including a first source/drain region, a body region, and a second source/drain region formed vertically on the substrate;

    forming a trench capacitor for each access transistor, each trench capacitor including a first plate formed integral with the first source/drain region of the respective access transistor and a second plate disposed adjacent to the first plate and separated therefrom by an insulator; and

    wherein forming the access transistors includes forming a first layer of material of a first conductivity type outwardly from the substrate, forming a second layer of material of a second conductivity type outwardly from the first layer, and forming a third layer of material of the first conductivity type outwardly from the second layer.

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