Circuit and method for an open bit line memory cell with a vertical transistor and trench plate trench capacitor

• US 6,537,871 B2
• Filed: 12/20/2000
• Issued: 03/25/2003
• Est. Priority Date: 10/06/1997
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Forbes, Leonard, Noble, Wendell P.
• Primary Examiner(s): Le, Vu A.
• Assistant Examiner(s): SMITH, BRADLEY
• Application Number:
  US09/742,568
• Publication Number:
  US 20010001722A1
• Time in Patent Office: 825 Days
• Field of Search: 438/301, 438/241, 438/336, 438/243, 438/244, 438/262, 438/239, 257/302, 257/301, 257/296
• US Class Current: 438/243
• CPC Class Codes: H10B 12/0383 wherein the transistor is vertical
• CPC Class Codes: H10B 12/395 the transistor being vertical

Abstract

A memory cell. The memory cell includes an access transistor. The access transistor is formed in a pillar of single crystal semiconductor material. The transistor has first and second source/drain regions and a body region that are vertically aligned. The memory cell also includes a body contact that is coupled to the body region. A gate of the transistor is disposed on a side of the pillar that is opposite from the body contact. A trench capacitor is also included. The trench capacitor includes a first plate that is formed integral with the first source/drain region of the access transistor and a second plate that is disposed adjacent to the first plate and separated from the first plate by a gate oxide. An insulator layer that separates the access transistor and the trench capacitor from an underlying layer of semiconductor material.

Claims

1. A method of fabricating an array of memory cells, comprising:

providing a substrate;

forming a plurality of access transistors, each access transistor formed in a pillar of semiconductor material extending outwardly from the substrate and including a first source/drain region, a body region, and a second source/drain region formed vertically on the substrate;

forming a trench capacitor for each access transistor, each trench capacitor including a first plate formed integral with the first source/drain region of the respective access transistor and a second plate disposed adjacent to the first plate and separated therefrom by an insulator; and

wherein forming the access transistors includes forming a first layer of material of a first conductivity type outwardly from the substrate, forming a second layer of material of a second conductivity type outwardly from the first layer, and forming a third layer of material of the first conductivity type outwardly from the second layer.

2. The method of claim 1, wherein forming the first layer of material includes forming a layer of N+ silicon by epitaxial growth, forming the second layer of material includes forming a layer of P−

silicon by epitaxial growth, and forming the third layer of material includes forming a layer of N+ silicon by ion implantation of dopant into the second layer of material.

3. A method of fabricating an array of memory cells, comprising:

providing a substrate;

forming a plurality of access transistors, each access transistor formed in a pillar of semiconductor material extending outwardly from the substrate and including a first source/drain region, a body region, and a second source/drain region formed vertically on the substrate;

forming a trench capacitor for each access transistor, each trench capacitor including a first plate formed integral with the first source/drain region of the respective access transistor and a second plate disposed adjacent to the first plate and separated therefrom by an insulator; and

wherein forming the plurality of access transistors includes forming column isolation trenches between adjacent columns of the access transistors and also includes forming row isolation trenches between adjacent rows of the access transistors.

4. The method of claim 3, wherein the pillar for each access transistor includes a first pair of opposite sides that are defined by adjacent column isolation trenches and a second pair of opposite sides that are defined by adjacent row isolation trenches.

5. A method of fabricating an array of memory cells, comprising:

providing a substrate;

forming a plurality of access transistors, each access transistor formed in a pillar of semiconductor material extending outwardly from the substrate and including a first source/drain region, a body region, and a second source/drain region formed vertically on the substrate;

forming a trench capacitor for each access transistor, each trench capacitor including a first plate formed integral with the first source/drain region of the respective access transistor and a second plate disposed adjacent to the first plate and separated therefrom by an insulator; and

wherein forming the plurality of access transistors includes forming column and row isolation trenches between adjacent columns and rows of the access transistors, respectively, and wherein forming the trench capacitor for each access transistor includes forming a conductive grid disposed in the column and row isolation trenches.

6. The method of claim 5, wherein forming the trench capacitor for each access transistor further includes forming an insulation layer between the grid and the respective pillar.

7. The method of claim 6, wherein forming the trench capacitor for each access transistor also includes forming an insulation layer between the substrate and each of the pillars.

8. A method of fabricating an array of memory cells, comprising:

providing a substrate;

forming a plurality of access transistors, each access transistor formed in a pillar of semiconductor material extending outwardly from the substrate and including a first source/drain region, a body region, and a second source/drain region formed vertically on the substrate, wherein forming the plurality of access transistors includes;

forming a first layer of material of a first conductivity type on the substrate,

forming a second layer of material of a second conductivity type on the first layer,

forming a third layer of material of the first conductivity type on the second layer,

forming column isolation trenches between adjacent columns of the access transistors, and

forming row isolation trenches between adjacent rows of the access transistors; and

forming a trench capacitor for each access transistor, each trench capacitor including a first plate formed integral with the first source/drain region of the respective access transistor and a second plate disposed adjacent to the first plate and separated therefrom by an insulator.

9. The method of claim 8, wherein forming the column isolation trenches includes etching through the first, second, and third layers of material by depositing a photoresist layer outwardly from the third layer, patterning the photoresist layer with a mask to define openings in the photoresist layer, and etching through the openings to form the column isolation trenches.

10. The method of claim 8, wherein forming the row isolation trenches includes depositing a layer of poly-silicon into the column isolation trenches, the layer of poly-silicon being recessed below a top surface of the first layer of material, and depositing a nitride layer outwardly from the recessed layer of poly-silicon.

11. The method of claim 10, wherein forming the row isolation trenches also includes depositing a layer of photoresist material outwardly from the nitride layer, and patterning the photoresist layer with a mask to define openings orthogonal to the column isolation trenches.

12. The method of claim 11, wherein forming the row isolation trenches also includes etching through the openings in the photoresist layer to expose a top surface of the third layer of material, wherein the layer of poly-silicon is still covered by a portion of the nitride layer, and then selectively etching portions of the first, second and third layers of material exposed in the openings down to a distance approximately equal to the depth of the column isolation trenches.

13. The method of claim 12, wherein forming the row isolation trenches also includes etching the portion of the nitride layer exposed in the openings to expose the poly-silicon layer, removing the photoresist layer, depositing a layer of poly-silicon through the openings to refill the column isolation trenches, and etching the layer of poly-silicon in the openings down to a distance approximately equal to the depth of the column isolation trenches.

14. A method of fabricating an array of memory cells, comprising:

providing a substrate;

forming a plurality of access transistors, each access transistor formed in a pillar of semiconductor material extending outwardly from the substrate and including a first source/drain region, a body region, and a second source/drain region formed vertically on the substrate, each pillar having a first pair of opposite sides defined by adjacent column isolation trenches and a second pair of opposite sides defined by adjacent row isolation trenches; and

forming a trench capacitor for each access transistor, each trench capacitor including a first plate formed integral with the first source/drain region of the respective access transistor and a second plate disposed adjacent to the first plate and separated therefrom by an insulator, the second plate being formed by a conductive grid in the column and row isolation trenches.

15. The method of claim 14, wherein forming the trench capacitor for each transistor includes forming an oxide layer between the pillars of semiconductor material and the substrate.

16. The method of claim 15, wherein forming the oxide layer includes etching the pillars of semiconductor material downwardly and laterally to completely undercut the pillars, and then forming the oxide layer in a region beneath the pillars of semiconductor material.

17. The method of claim 16, wherein etching the pillars of semiconductor material downwardly and laterally includes performing an isotropic silicon etch.

18. The method of claim 16, wherein etching the pillars of semiconductor material includes supporting the pillars by contact with original crystals at the ends of the pillars.

19. The method of claim 16, wherein forming the oxide layer in the region beneath the pillars includes growing the oxide layer with a thickness of approximately 0.1 micrometers.

20. The method of claim 15, wherein forming the trench capacitor for each access transistor includes electrically separating the conductive grid from the first source/drain region of each access transistor using both the insulator and the oxide layer.

21. The method of claim 14, wherein forming the grid includes forming an oxide layer in the row isolation trenches, etching the oxide layer to expose the underlying substrate, depositing a conductive material onto the exposed substrate to form a conductive contact, forming an insulator layer in the column and row isolation trenches, etching the insulator layer to remove the insulator layer from the bottom of the row isolation trenches to expose the conductive contact, and depositing a conductive material in the column and row isolation trenches to form the grid, wherein the grid surrounds the pillar that forms each of the access transistors.

22. A method of fabricating an array of memory cells, comprising:

providing a substrate;

forming a plurality of access transistors, each access transistor formed in a pillar of semiconductor material extending outwardly from the substrate and including a first source/drain region, a body region, and a second source/drain region formed vertically on the substrate, each pillar having a first pair of opposite sides defined by adjacent column isolation trenches and a second pair of opposite sides defined by adjacent row isolation trenches;

forming a trench capacitor for each access transistor, each trench capacitor including a first plate formed integral with the first source/drain region of the respective access transistor and a second plate disposed adjacent to the first plate and separated therefrom by an insulator; and

forming a plurality of body address lines in the row isolation trenches, wherein each body address line interconnects the body regions of access transistors that form a row of the array.

23. The method of claim 22, wherein forming the body address lines includes depositing a nitride layer into the row isolation trenches, depositing a photoresist layer onto the nitride layer, patterning the photoresist layer using a mask to define openings exposing a portion of each row isolation trench, etching through the openings to the body regions of the pillars, depositing a layer of conductive material, and etching the conductive material to form the body address lines so that the body address lines are in electrical contact with the body regions.

24. A method of fabricating an array of memory cells, comprising:

providing a substrate;

forming a plurality of access transistors, each access transistor formed in a pillar of semiconductor material extending outwardly from the substrate and including a first source/drain region, a body region, and a second source/drain region formed vertically on the substrate, wherein forming the access transistors includes forming a first layer of material of a first conductivity type on the substrate, forming a second layer of material of a second conductivity type on the first layer, forming a third layer of material of the first conductivity type on the second layer, forming column isolation trenches between adjacent columns of the access transistors, and forming row isolation trenches between adjacent rows of the access transistors;

forming a trench capacitor for each access transistor, each trench capacitor including a first plate formed integral with the first source/drain region of the respective access transistor and a second plate disposed adjacent to the first plate and separated therefrom by an insulator;

forming a plurality of word lines disposed in the row isolation trenches, wherein each word line interconnects gates of a plurality of access transistors that form a row of the array;

forming a plurality of body address lines in the row isolation trenches, wherein each body address line interconnects the body regions of access transistors that form a row of the array; and

forming a plurality of bit lines interconnecting the second source/drain regions of a plurality of access transistors that form a column of the array.