Process for fabricating a non-volatile memory device

• US 6,537,881 B1
• Filed: 10/16/2000
• Issued: 03/25/2003
• Est. Priority Date: 10/16/2000
• Status: Expired due to Term

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Park, Steven K., Rangarajan, Bharath, Foote, David, Wang, Fei
• Primary Examiner(s): FOURSON III, GEORGE R
• Application Number:
  US09/688,504
• Time in Patent Office: 890 Days
• Field of Search: 438/257, 438/261, 438/763, 438/792, 438/795, 438/FOR.203, 438/FOR.333, 438/FOR.334, 438/FOR.401, 438/FOR.434, 438/4, 438/516, 438/216, 438/591, 438/FOR.202
• US Class Current: 438/261
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H10B 43/30 characterised by the memory core region

Abstract

A process for fabricating a non-volatile memory device in which extraneous electrical charge is removed from charge-storage layers during fabrication includes exposing a charge-storage layer to infrared radiation prior to forming additional layers of the non-volatile memory cell. For example, in a memory cell incorporating a dielectric floating-gate electrode, such as silicon nitride, the infrared radiation exposure step is carried out after forming the floating-gate electrodes and prior to formation of the control-gate electrode. By exposing the charge-storage layer to infrared radiation prior to forming additional layers, extraneous electrical charge arising from previous processing steps can be efficiently removed from the floating-gate electrodes.

Claims

1. A process for fabricating a non-volatile memory device comprising the steps of:

providing a semiconductor substrate;

forming a charge-storage layer overlying the semiconductor substrate;

wherein the charge-storage layer has an exposed surface region;

forming a buried bit-line in the semiconductor substrate; and

after the buried bit-line is formed, bombarding the exposed surface region with sufficient infrared radiation to remove unwanted electrical charge from the charge-storage layer.

2. The process of claim 1, wherein the step of forming a charge-storage layer comprises forming an silicon nitride layer.

3. The process of claim 1, wherein the step of forming a charge-storage layer comprises the steps of:

forming a first silicon oxide layer overlying the substrate;

forming a silicon nitride layer overlying the first silicon oxide layer; and

forming a second silicon oxide layer overlying the silicon nitride layer.

4. The process of claim 3, wherein the step of bombarding the charge-storage layer with infrared radiation comprises removing unwanted electrical charge from the silicon nitride layer.

5. The process of claim 1, wherein the step of forming the charge-storage layer comprises the steps of:

chemical vapor depositing an ONO layer;

forming a resist pattern on the ONO layer; and

plasma etching the ONO layer.

6. The process of claim 1, wherein the step of bombarding the exposed surface region with infrared radiation comprises using infrared radiation having a wavelength of about 600 nm to about 1100 nm.

7. The process of claim 1, wherein the process of forming a charge-storage layer comprises forming a polycrystalline silicon layer.

8. The process of claim 1, further comprising the step of forming a control gate electrode overlying the charge-storage layer.

9. A process for fabricating a non-volatile memory device comprising the steps of:

providing a semiconductor substrate;

forming a change-storage layer overlying the semiconductor substrate;

forming a resist pattern on the charge-storage layer;

etching the charge-storage layer;

removing the resist pattern;

forming a buried bit-line in the semiconductor substrate; and

after the buried bit-line is formed, exposing the charge-storage layer to sufficient infrared radiation to remove unwanted electrical charge from the charge-storage layer.

10. The process of claim 9, wherein the step of forming a charge-storage layer comprises forming a silicon nitride layer.

11. The process of claim 9, wherein the step of forming a charge-storage layer comprises forming a polycrystalline silicon layer.

12. The process of claim 9 further comprising the step of forming a control-gate electrode overlying the charge-storage layer.

13. The process of claim 12, wherein the step of forming a control-gate electrode comprises forming an insulating layer;

and

forming a layer of polycrystalline silicon layer overlying the insulating layer.

14. The process of claim 9, wherein the step of etching the charge-storage layer exposes surface regions of the semiconductor substrate and wherein the process further comprises the step of forming bit-line oxide regions on the semiconductor substrate prior to the step of exposing the charge-storage layer to infrared radiation.

15. A process for fabricating a non-volatile semiconductor device comprising the steps of:

providing a semiconductor substrate;

forming a charge-storage layer overlying the semiconductor substrate;

forming a buried bit-line in the semiconductor substrate;

after the buried bit-line is formed, exposing the charge-storage layer to sufficient infrared radiation to remove unwanted electrical charge from the charge-storage layer; and

forming a control-gate layer overlying the charge-storage layer.

16. The process of claim 15 wherein the step of forming a charge-storage layer comprises forming a patterned charge storage layer on a portion of the semiconductor substrate and leaving an exposed portion of the substrate, and wherein the process further comprises forming an oxide region in the exposed portion of the substrate.

17. The process of claim 15, wherein the step of forming a charge-storage layer comprises depositing a layer selected from the group consisting of silicon nitride and polycrystalline silicon.

18. The process of claim 15, wherein the step of forming a charge-storage layer comprises forming a layer having process-induced electrical charge therein.