Amplified CMOS transducer for single photon read-out of photodetectors

• US 6,538,245 B1
• Filed: 10/26/2000
• Issued: 03/25/2003
• Est. Priority Date: 10/26/2000
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Rockwell Science Center LLC
• Inventors: Kozlowski, Lester J.
• Primary Examiner(s): Pyo, Kevin
• Assistant Examiner(s): Sohn, Seung C.
• Application Number:
  US09/696,919
• Time in Patent Office: 880 Days
• Field of Search: 250/214.A, 250/214.LA, 250/208.1, 250/214.R, 330/59, 330/308, 257/290-292, 377/60, 348/294, 348/297, 348/300, 348/301, 348/308
• US Class Current: 250/208.1
• CPC Class Codes: H03F 2200/162 FETs are biased in the weak inversion region
• CPC Class Codes: H03F 3/082 with FET's H03F3/085 takes precedence
• CPC Class Codes: H04N 25/616 involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
• CPC Class Codes: H04N 25/65 applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS
• CPC Class Codes: H04N 25/771 comprising storage means other than floating diffusion
• CPC Class Codes: H04N 25/773 comprising photon counting circuits, e.g. single photon detection [SPD] or single photon avalanche diodes [SPAD]
• CPC Class Codes: H04N 25/78 Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

Abstract

An ultra-low noise, high-gain interface pixel amplifier is provided with capability for single-photon readout of known photodetectors at high electrical bandwidths for diverse spectral bandpass from the x-ray to long IR bands. The detector charge modulates a source follower whose output is double sampled to remove correlated noise by a compact stage that also facilitates low-noise gain adjustment for a second gain stage of programmable amplification. Single-photon readout of photodetectors at high electrical bandwidths in small pixel areas is thereby facilitated.

Claims

1. A single-photon read-out circuit, comprising:

a photodetector producing a photodetector output signal;

a buffer amplifier, arranged to receive the photodetector output signal, having a buffered photodetector output signal;

a signal amplifier having a signal input and a signal output;

a coupling capacitor, having a first terminal connected to the buffered output signal and a second terminal connected to the signal input of the signal amplifier;

an electronic offset reset switch, connected to the coupling capacitor; and

a synchronization circuit connected to an input of the buffer amplifier and to the signal output of the signal amplifier.

2. The circuit of claim 1, further comprising an integration capacitor connected to the signal output of the signal amplifier.

3. The circuit of claim 2, further comprising a sample-and-hold circuit connected to the signal output of the signal amplifier.

4. The circuit of claim 3, further comprising an output amplifier connected to the sample-and-hold circuit.

5. The circuit of claim 4, further comprising a variable current source connected to the signal amplifier.

6. The circuit of claim 5, wherein the buffer amplifier comprises two MOSFETs arranged in a source follower configuration.

7. The circuit of claim 6, wherein the signal amplifier comprises a MOSFET.

8. The circuit of claim 7, wherein the offset reset switch comprises a MOSFET.

9. The circuit of claim 8, wherein the synchronization circuit comprises two MOSFETs having a reset signal connected to each gate.

10. The circuit of claim 9, wherein the sample-and-hold circuit comprises a MOSFET and a capacitor.

11. The circuit of claim 10, wherein the variable current source comprises a MOSFET and a capacitor.

12. A single-photon read-out circuit, comprising:

a photodetector that integrates a small-signal photocharge on a detector capacitance in response to incident photons, producing a photodetector output signal;

a buffer amplifier, arranged to receive the photodetector output signal and to produce a buffered photodetector output signal;

a signal amplifier having a signal input and producing a signal output;

a coupling capacitor, having a first terminal connected to the buffered output signal and a second terminal connected to the signal input of the signal amplifier, to shift a signal level by an offset voltage;

an electronic offset reset switch, connected to the coupling capacitor, for resetting the offset voltage; and

a synchronization circuit connected to an input of the buffer amplifier and to the output signal of the signal amplifier to synchronize a start of signal integration across a pixellated array.

13. The circuit of claim 12, further comprising a sample-and-hold circuit for storing a signal voltage.

14. The circuit of claim 13, further comprising a variable current source connected to the signal amplifier for increasing an instantaneous dynamic range of the circuit.

15. A signal read-out circuit comprising:

a photodetector connected to a detector voltage;

a first MOSFET having a gate connected to the photodetector, and a drain connected to a first voltage;

a second MOSFET having a drain connected to a source of the first MOSFET, and a gate connected to a first bias voltage;

a correlated double sampling capacitor having a first terminal connected to the source of the first MOSFET;

a signal amplifier MOSFET having a gate connected to a second terminal of the correlated double sampling capacitor, and a source connected to a second voltage;

an electronic offset reset switch MOSFET having a source connected to the second terminal of the correlated double sampling capacitor, a drain connected to a gain voltage, and a gate connected to a correlated double sampling signal;

an integration capacitor connected to the drain of the signal amplifier MOSFET;

a sample-and-hold MOSFET having a source connected to the drain of the signal amplifier MOSFET, and a gate connected to a sample-and-hold signal; and

a sample-and-hold capacitor connected to a drain of the sample-and-hold MOSFET.

16. The circuit of claim 15, further comprising:

a first reset MOSFET having a drain connected to the gate of the first MOSFET, a gate connected to a reset signal, and a source connected to a detector reset voltage; and

a second reset MOSFET having a drain connected to the drain of the signal amplifier, a gate connected to the reset signal, and a source connected to a cell reset voltage.

17. The circuit of claim 16, further comprising:

an amplifier MOSFET having a source connected to a buffer voltage, a gate connected to the drain of the sample-and-hold MOSFET; and

an access MOSFET having a source connected to a drain of the amplifier MOSFET, a gate connected to an access signal, and a drain connected to a bus.

18. The circuit of claim 15, further comprising:

a dynamic range MOSFET having a drain connected to the source of the signal amplifier MOSFET, a source connected to a source voltage, and a gate connected to a dynamic range signal; and

a dynamic range capacitor connected to the drain of the dynamic range MOSFET.

19. A single-photon read-out circuit, comprising:

a photodetector producing a photodetector output signal current;

a buffer amplifier, arranged to receive the photodetector output signal current, having a buffered photodetector output signal;

a coupling capacitor, having a first terminal connected to the buffered output signal;

a variable gain signal amplifier having a signal input connected to the coupling capacitor and a signal output connected to an integration capacitor; and

an electronic offset reset switch having a variable reset level, connected to the coupling capacitor;

wherein the integration capacitor integrates an amplified facsimile of the photodetector output signal current, and wherein the electronic offset reset switch adjusts signal amplification in the variable gain signal amplifier.

20. The circuit of claim 19, further comprising a synchronization circuit connected to an input of the buffer amplifier and to the signal output of the variable gain signal amplifier.

21. The circuit of claim 20, further comprising a sample-and-hold circuit connected to the signal output of the variable gain signal amplifier.

22. The circuit of claim 21, further comprising an output amplifier connected to the sample-and-hold circuit.

23. The circuit of claim 22, further comprising a variable current source connected to the variable gain signal amplifier.

24. The circuit of claim 23, wherein the buffer amplifier comprises two MOSFETs arranged in a source follower configuration.

25. The circuit of claim 24, wherein the variable gain signal amplifier comprises a MOSFET.

26. The circuit of claim 25, wherein the offset reset switch comprises a MOSFET.

27. The circuit of claim 26, wherein the synchronization circuit comprises two MOSFETs having a reset signal connected to each gate.

28. The circuit of claim 27, wherein the sample-and-hold circuit comprises a MOSFET and a capacitor.

29. The circuit of claim 28, wherein the variable current source comprises a MOSFET and a capacitor.

30. A single-photon read-out circuit, comprising:

a photodetector that integrates a small-signal photocharge on a detector capacitance in response to incident photons, producing a photodetector output signal current;

a buffer amplifier, arranged to receive the photodetector output signal current and to produce a buffered photodetector output signal;

a coupling capacitor, having a first terminal and a second terminal, the first terminal connected to the buffered output signal, wherein the coupling capacitor shifts a DC level of the buffered photodetector output signal;

a variable gain signal amplifier having a signal input connected to the coupling capacitor and a signal output connected to an integration capacitor, wherein the integration capacitor integrates an amplified facsimile of the photodetector output signal current; and

an electronic offset reset switch, connected to the coupling capacitor, for variably resetting the offset voltage to modify the gain of the variable gain signal amplifier.

31. The circuit of claim 30, further comprising a synchronization circuit connected to an input of the buffer amplifier and to the output signal of the variable gain signal amplifier to synchronize a start of signal integration across a pixellated array.

32. The circuit of claim 31, further comprising a sample-and-hold circuit for storing a signal voltage.

33. The circuit of claim 32, further comprising a variable current source connected to the signal amplifier for increasing an instantaneous dynamic range of the circuit.

34. A signal read-out circuit comprising:

a photodetector connected to a detector voltage;

a first MOSFET having a gate connected to the photodetector, and a drain connected to a first voltage;

a second MOSFET having a drain connected to a source of the first MOSFET, and a gate connected to a first bias voltage;

a correlated double sampling capacitor having a first terminal connected to the source of the first MOSFET;

a signal amplifier MOSFET having a gate connected to a second terminal of the correlated double sampling capacitor, and a source connected to a variable voltage;

an electronic offset reset switch MOSFET having a source connected to the second terminal of the correlated double sampling capacitor, a drain connected to a variable reset voltage, and a gate connected to a correlated double sampling signal; and

an integration capacitor connected to the drain of the signal amplifier MOSFET, wherein the integration capacitor integrates an amplified facsimile of a signal current from the photodetector.

35. The circuit of claim 34, further comprising:

a sample-and-hold MOSFET having a source connected to the drain of the signal amplifier MOSFET, and a gate connected to a sample-and-hold signal; and

a sample-and-hold capacitor connected to a drain of the sample-and-hold MOSFET.

36. The circuit of claim 35, further comprising:

a first reset MOSFET having a drain connected to the gate of the first MOSFET, a gate connected to a reset signal, and a source connected to a detector reset voltage; and

a second reset MOSFET having a drain connected to the drain of the signal amplifier, a gate connected to the reset signal, and a source connected to a cell reset voltage.

37. The circuit of claim 36, further comprising:

an amplifier MOSFET having a source connected to a buffer voltage, a gate connected to the drain of the sample-and-hold MOSFET; and

an access MOSFET having a source connected to a drain of the amplifier MOSFET, a gate connected to an access signal, and a drain connected to a bus.

38. The circuit of claim 34, further comprising:

a dynamic range MOSFET having a drain connected to the source of the signal amplifier MOSFET, a source connected to a source voltage, and a gate connected to a dynamic range signal; and

a dynamic range capacitor connected to the drain of the dynamic range MOSFET.