Static protection device

• US 6,538,290 B1
• Filed: 01/27/2000
• Issued: 03/25/2003
• Est. Priority Date: 01/28/1999
• Status: Expired due to Fees

• Current Assignee: Mitsumi Electric Co., Ltd. (MinebeaMitsumi Inc.)
• Original Assignee: Mitsumi Electric Co., Ltd. (MinebeaMitsumi Inc.)
• Inventors: Terada, Yukihiro, Ishikawa, Yasuhisa
• Primary Examiner(s): ECKERT II, GEORGE C
• Application Number:
  US09/492,072
• Time in Patent Office: 1,153 Days
• Field of Search: 257/355, 257/361, 257/362, 257/546, 361/100, 361/101
• US Class Current: 257/362
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 29/735 Lateral transistors

Abstract

A static protection device protects an internal circuit of a semiconductor device from surge voltages. An emitter terminal of the PNP transistor is connected to the input/output terminal, a collector terminal of the PNP transistor is connected to the ground terminal, and the base terminal is left open, to realize the static protection device. In this manner the reverse-biased protection can be maintained with respect to the internal circuit.

Claims

1. A static protection device for an integrated semiconductor device comprising:

an input/output terminal for the integrated semiconductor device;

a ground terminal for the integrated semiconductor device; and

a PNP transistor formed in the integrated semiconductor device and connected between the input/output terminal and the ground terminal,

wherein the PNP transistor is formed in an N-type conductivity layer on a P-type substrate between first and second isolation regions and comprises a first P-type diffusion region formed in the N-type conductivity layer between the first and second isolation regions and forming an emitter terminal of the PNP) transistor connected to the input/output terminal, and a second P-type diffusion region formed on the second isolation region and contacting the N-type conductivity layer between the first and second isolation regions and forming a collector terminal of the PNP transistor connected to the ground terminal.

2. The static protection device for an integrated semiconductor device as set forth in claim 1, wherein a buried layer having N⁺-type conductivity is formed below the first P-type diffused region comprising the emitter terminal of the PNP transistor.

3. The integrated semiconductor device as set forth in claim 2, wherein a region having N⁺-type conductivity is formed in the vicinity of the surface of the semiconductor layer having N-type conductivity so as to surround the first P-type diffused region comprising the emitter terminal of the PNP transistor.

4. The static protection device for an integrated semiconductor device as set forth in claim 1, wherein a region having N⁺-type conductivity is formed in the vicinity of the surface of the N-type conductivity layer so as to surround the first P-type diffused region comprising the emitter terminal of the PNP transistor.

5. An integrated semiconductor device comprising:

an input/output terminal for an internal circuit of the integrated semiconductor device;

a ground terminal;

a semiconductor substrate having P-type conductivity;

a semiconductor layer having N-type conductivity, which is formed in the vicinity of the surface of the semiconductor substrate;

first and second isolation regions formed laterally in the semiconductor layer and extending to the semiconductor substrate, which provide element separation; and

first and second diffused regions having P-type conductivity formed laterally in the vicinity of the surface of the semiconductor layer having N-type conductivity, the first diffused region being formed between said first and second isolation regions and the second diffused region being formed on said second isolation region and contacting the semiconductor layer between the first and second isolation regions;

wherein a PNP transistor is formed in which the first P-type diffused region is used for an emitter terminal connected to the input/output terminal, and the second P-type diffused region is used for a collector terminal connected to the ground terminal, the PNP transistor having a base terminal being left open.

6. The integrated semiconductor device as set forth in claim 5, wherein a buried layer having N+-type conductivity is formed below the first P-type diffused region comprising the emitter terminal of the PNP transistor.

7. The integrated semiconductor device as set forth in claim 6, wherein a region having N⁺-type conductivity is formed in the vicinity of the surface of the semiconductor layer having N-type conductivity so as to surround the first P-type diffused region comprising the emitter terminal of the PNP transistor.

8. The integrated semiconductor device as set forth in claim 5, wherein a region have N⁺-type conductivity is formed in the vicinity of the surface of the semiconductor layer having N-type conductivity so as to surround the first P-type diffused region comprising the emmitter terminal of the PNP transistor.