Three dimensional IC package module

• US 6,538,333 B2
• Filed: 06/11/2002
• Issued: 03/25/2003
• Est. Priority Date: 06/16/2000
• Status: Expired due to Term

• Current Assignee: Chartered Semiconductor Manufacturing Incorporated (Mamoura Diversified Global Holding PJSC)
• Original Assignee: Chartered Semiconductor Manufacturing Incorporated (Mamoura Diversified Global Holding PJSC)
• Inventors: Kong, Sik On
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Le, Thao P
• Application Number:
  US10/167,861
• Publication Number:
  US 20020155692A1
• Time in Patent Office: 287 Days
• Field of Search: 257/675, 257/686, 257/706, 257/777, 257/778, 257/796
• US Class Current: 257/777
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06555 Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

In the present invention a high performance package is described where semiconductor chips are stacked together in a pancake like fashion with inter chip communications facilitated by chip to chip vias formed through the material of each chip. The chip to chip vias are created by etching and filling a hole from the back of a chip through the silicon substrate stopping at the first level of metalization and invoking the wiring of the chip to complete the path to the top side. The chip in the stack are aligned so that chip to chip vias form columns. Signal and power can travel the full length of a column from the bottom chip to the chip on top, or the wiring within the chips can interrupt the signal flow and form interstitial connections. Interstitial connections can also be used to enhance the wireability between chips in the stack. To accomodate cooling the chips in the stack are made in varying sizes and are ordered in size from the largest at the bottom of the stack to the smallest at the top of the stack. This provides a stair case like structure to allow heat sinks to be attached to each step formed by a chip and the smaller chip above. An interface substrate sits at the bottom of the stack and provides for communication external to the stack by connecting the columns of chip to chip vias to an array of pins to mate with a connector. The short distances that signals must travel lends this three dimensional stacked chip package to high performance for off chip communications.

Claims

1. A three dimensional integrated circuit module, comprising:

a) a number of unequal size semiconductor chips forming a chip stack where said semiconductor chips are stacked back side to front side and ordred by size from a largest chip at a bottom of said stack to a smallest chip at a top of said stack where each larger chip has an area extending out beyond a subsequent smaller chip in a stair case fashion.

b) back side of said largest chip stacked to a front side of a substrate larger than said largest chip,

c) a first solder pad array located on said front side of said chips electrically connected to internal chip wiring and aligned with a second solder pad array on said back side of said chips electrically connected to said internal wiring of said chips,

d) said first solder pad array on the front side of said larger chip in the stack aligned with and connected to said second solder pad array located on the back side of a smaller chip positioned above and adjacent to said larger chip in said stack,

e) a pin array on back side of said substrate connected to a third solder pad array on said front side of said substrate that is aligned with and connected to said second solder pad array on back side of said largest chip,

f) said pin array on back side of said substrate connects power and ground, and input and output signals to said semiconductor chips,

g) a set of solder pads connected to a heat sink to provide cooling to said chips located in the area extending beyond said subsequent smaller chip in said chip stack.

2. The module of claim 1, wherein electrical connections can be continuous from said pin array on said substrate to internal wiring of said smallest chip at top of said chip stack.

3. The module of claim 2, wherein electrical connections made noncontinuous from said pin array through the pad array of each chip to said smallest chip at top of said chip stack provides for interstitial connections between circuits in said chip stack.

4. The module of claim 1, wherein individual heat sinks are connected to said set of solder pads at edge of each chip to provide additional cooling to said chips.

5. The module of claim 1, wherein said pin array on said substrate is larger than said solder pad array on said chips to accommodate a connector system where said substrate redistributes connections between said pin array and said solder pad array.

6. The module of claim 1, wherein all chips are a same size, without said heat sink and attached to a substrate adequately sized to accommodate said pin array.