High density flip chip memory arrays

• US 6,538,334 B2
• Filed: 06/15/2001
• Issued: 03/25/2003
• Est. Priority Date: 03/25/1998
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Farnworth, Warren M., Wood, Alan G., Akram, Salman
• Primary Examiner(s): Abraham, Fetsum
• Application Number:
  US09/881,792
• Publication Number:
  US 20010030371A1
• Time in Patent Office: 648 Days
• Field of Search: 257/296-315, 257/778, 257/777
• US Class Current: 257/778
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05027 the internal layer extending out of an opening
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/0615 Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/1319 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/274 by blanket deposition of the material of the layer connector
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 23/556 against alpha rays
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/0105 Tin [Sn]
• CPC Class Codes: H01L 2924/01075 Rhenium [Re]
• CPC Class Codes: H01L 2924/01082 Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H10B 12/50 : Peripheral circuit region structures

Abstract

A low alpha emissivity-induced error solder bump, flip-chip integrated circuit device. The device includes a semiconductor die having an active surface and a bond pad array disposed about the active surface of the die. The active surface of the die includes logic circuits adjacent memory cell arrays. Each of the bond pads directly overlays a logic circuit, to which they may be connected. The present invention also includes methods for designing and fabricating the invented devices and connecting them to a carrier substrate.

Claims

1. An integrated circuit device, comprising:

at least one memory cell array;

at least one circuit trace comprising at least one of a column decoder and a row decoder positioned adjacent to at least one memory cell of said at least one memory cell array; and

an array of bond pads on an active surface of the integrated circuit device, at least a portion of at least one bond pad of said array of bond pads being located over said at least one circuit trace.

2. The integrated circuit device of claim 1, wherein said at least one bond pad is in communication with said at least one circuit trace.

3. The integrated circuit device of claim 2, wherein said at least one bond pad contacts said at least one circuit trace.

4. The integrated circuit device of claim 1, wherein said at least one bond pad is laterally offset from said at least one memory cell.

5. The integrated circuit device of claim 1, wherein each bond pad thereof is laterally offset from memory cells thereof.

6. The integrated circuit device of claim 1, wherein the integrated circuit device comprises a dynamic random access memory device.

7. The integrated circuit device of claim 1, further comprising:

discrete conductive elements positioned on at least some bond pads of said array of bond pads.

8. The integrated circuit device of claim 7, further comprising:

a protective layer over at least a portion of said active surface and laterally surrounding each discrete conductive element such that each discrete conductive element protrudes from said protective layer.

9. The integrated circuit device of claim 1, further comprising:

a protective layer over at least a portion of said active surface, at least some bond pads of said array of bond pads being electrically exposed through said protective layer.

10. A dynamic random access memory device, comprising:

a plurality of memory cell arrays;

a plurality of circuit traces, each circuit trace of said plurality of circuit traces comprising at least one of a column decoder and a row decoder; and

a plurality of bond pads located on an active surface of the dynamic random access memory device, each of said plurality of bond pads overlying a corresponding circuit trace of said plurality of circuit traces and associated with a corresponding circuit trace.

11. The dynamic random access memory device of claim 10, wherein each of said plurality of bond pads overlies and is associated with the same corresponding circuit trace of said plurality of circuit traces.

12. The dynamic random access memory device of claim 10, further comprising:

discrete conductive elements positioned on at least some bond pads of said plurality of bond pads.

13. The dynamic random access memory device of claim 12, further comprising:

a protective layer over at least a portion of said active surface and laterally surrounding each discrete conductive element such that each discrete conductive element protrudes from said protective layer.

14. The dynamic random access memory device of claim 10, further comprising:

a protective layer over at least a portion of said active surface, at least some bond pads of said plurality of bond pads being electrically exposed through said protective layer.

15. The dynamic random access memory device of claim 10, wherein every bond pad thereof at least partially overlies a circuit trace of said plurality of circuit traces.

16. An integrated circuit device, comprising:

a memory cell array;

at least one circuit element positioned between adjacent memory cells of said memory cell array; and

at least one bond pad located on an active surface of the integrated circuit device, at least a portion of said at least one bond pad being positioned at least partially over said at least one circuit element.

17. The integrated circuit device of claim 16, wherein said at least one bond pad is in communication with said at least one circuit element.

18. The integrated circuit device of claim 16, wherein said at least one bond pad directly overlies said at least one circuit element.

19. The integrated circuit device of claim 16, wherein said at least one bond pad is laterally offset from said memory cell array.

20. The integrated circuit device of claim 16, wherein the integrated circuit device comprises a dynamic random access memory device.

21. The integrated circuit device of claim 16, wherein each bond pad thereof is positioned at least partially over a circuit element.

22. A flip chip type semiconductor device, comprising:

a memory cell array;

at least one circuit element comprising at least one of a column decoder and a row decoder; and

at least one discrete external connective element disposed on an active surface of said semiconductor device, at least a portion of said at least one discrete external connective element being positioned over said at least one circuit element.

23. The flip chip type semiconductor device of claim 22, wherein said at least one discrete external connective element is laterally offset from memory cells of said memory cell array.

24. The flip chip type semiconductor device of claim 22, wherein each discrete external connective element thereof is laterally offset from memory cells of said memory cell array.

25. A semiconductor device, comprising:

at least one active memory element;

at least one nonmemory circuit comprising at least one of a column decoder and a row decoder positioned laterally adjacent said at least one active memory element; and

at least one bond pad positioned substantially vertically over said at least one nonmemory circuit.

26. The semiconductor device of claim 25, further comprising at least one electrically conductive structure protruding from said at least one bond pad.

27. The semiconductor device of claim 25, wherein said at least one bond pad is in communication with said at least one nonmemory circuit.

28. The semiconductor device of claim 25, wherein said at least one bond pad is laterally offset from said at least one active memory element.

29. The semiconductor device of claim 25, wherein each bond pad thereof is laterally offset from active memory elements thereof.