Technique to test an integrated circuit using fewer pins
First Claim
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1. A programmable logic circuit comprising:
- an array of logic blocks arranged in rows and columns;
an interconnect structure comprising first conductors between columns of the logic blocks and second conductors between rows of the logic blocks;
a plurality of test pins to interface with signals external to the programmable circuit, wherein each of the test pins provides test data to at least two columns of logic blocks;
a first register for two columns of logic blocks, wherein test data is loaded into the first register via one test pin; and
a second register for two columns of logic blocks, wherein test data stored in the first register is loaded into the second register in parallel.
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Abstract
A technique to implement functions requiring fewer pins of an integrated circuit to serially transfer data into the integrated circuit for multiple logic blocks. By reducing the required pins, this permits downbonding of the integrated circuit into a package with fewer pins. This technique may be used to implement test Functions in a programmable logic device. Test data may be serially input using a test pin (410) for two or more columns (320) of logic blocks. The test data is stored in an A resister (330), and may be later transferred into a B register (335).
57 Citations
35 Claims
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1. A programmable logic circuit comprising:
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an array of logic blocks arranged in rows and columns;
an interconnect structure comprising first conductors between columns of the logic blocks and second conductors between rows of the logic blocks;
a plurality of test pins to interface with signals external to the programmable circuit, wherein each of the test pins provides test data to at least two columns of logic blocks;
a first register for two columns of logic blocks, wherein test data is loaded into the first register via one test pin; and
a second register for two columns of logic blocks, wherein test data stored in the first register is loaded into the second register in parallel.
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2. A programmable logic circuit comprising:
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an array of logic blocks arranged in rows and columns;
an interconnect structure comprising first conductors between columns of the logic blocks and second conductors between rows of the logic blocks;
a plurality of test pins to interface with signals external to the programmable circuit, wherein each of the test pins provides test data to at least two columns of logic blocks;
a fist multiplexer coupled to selectively pass a first signal from a test pin or a second signal to a first multiplexer output;
a first flip-flop, coupled to the first multiplexer output;
a second flip-flop, coupled to a first flip-flop output; and
a second multiplexer, coupled to a second flip-flop output, a second multiplexer output coupled to a logic block. - View Dependent Claims (3, 4, 30)
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5. A programmable logic circuit comprising:
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a plurality of logic array blocks arranged in rows and columns;
an interconnect structure comprising a first plurality of conductors between columns of the logic array blocks and a second plurality of conductors between the rows of the logic array blocks;
a plurality of test pins;
a first plurality of registers, each selectively coupled to one of the plurality of test pins; and
a second plurality of registers, each coupled between one of the first plurality of registers and a column of logic array blocks. - View Dependent Claims (6, 7, 8, 31, 32)
a plurality of flip-flops arranged in a serial chain, a first flip-flop in the serial chain selectively coupled to one of the plurality of test pins.
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31. The programmable logic circuit of claim 5 wherein each of the second plurality of registers flier couple to another column of logic array blocks.
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32. The programmable logic circuit of claim 8 wherein each of the second plurality of registers comprises:
a plurality of flip-flips, each flip-flop coupled to a FIFO chain in the column of logic array blocks.
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9. A programmable logic circuit comprising:
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a plurality of logic array blocks arranged in rows and columns;
an interconnect structure comprising a first plurality of conductors between columns of the logic array blocks and a second plurality of conductors between the rows of the logic array blocks;
a test pin;
a first register selectively coupled to the test pin; and
a second register coupled between the first register and at least two columns of logic array blocks. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17, 33, 34)
a multiplexer having a first input, a second input, and an output, wherein the first input is coupled to an output of the first flip-flop in the second register and the second input is coupled to an inverting output of the first flip-flop in the second register.
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17. The programmable logic circuit of claim 15 further comprising:
a multiplexer having a first input, a second input, and an output, wherein the first input is coupled to the test pin and the output is coupled to the first flip-flop in the first register.
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33. The programmable logic circuit of claim 9 wherein the second register is coupled to a plurality of FIFO chains in the columns of logic array blocks.
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34. The programmable logic circuit of claim 15 wherein the first flip-flop in the second register is coupled to a FIFO in one of the columns of logic array blocks.
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18. A programmable logic circuit comprising:
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a plurality of logic array blocks arranged in rows and columns;
an interconnect structure comprising a first plurality of conductors between columns of the logic array blocks and a second plurality of conductors between the rows of the logic array blocks;
a test pin;
a first flip-flop having an input coupled to the test pin, a clock input, and an output;
a second flip-flop having an input coupled to the output of the first flip-flop, a clock input, and an output;
a third flip-flop having an input coupled to the output of the first flip-flop, a clock input, and an output coupled to a column of logic array blocks; and
a fourth flip-flop having an input coupled to the output of the second flip-flop, a clock input, and an output coupled to the column of logic array blocks. - View Dependent Claims (19, 20)
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21. A programmable logic circuit comprising:
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a plurality of logic array blocks arranged in rows and columns;
an interconnect structure comprising a first plurality of conductors between columns of the logic array blocks and a second plurality of conductors between the rows of the logic array blocks;
a test pin;
a shift register having an input coupled to the test pin; and
a parallel register having inputs coupled to outputs of the shift register, and outputs coupled to at least one column of logic array blocks. - View Dependent Claims (22, 23, 25, 26, 27, 35)
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24. An integrated circuit comprising:
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an array of logic blocks arranged in rows and columns;
a plurality of test pins, wherein each of the test pins receives test data for at least one column of logic blocks;
a fist register, wherein test data is loaded into the first register serially via a test pin; and
a second register, wherein test data stored in the first register is loaded into the second register in parallel.
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28. An integrated circuit comprising:
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an array of logic blocks arranged in rows and columns;
an interconnect structure comprising fist conductors between columns of the logic blocks and second conductors between rows of the logic blocks;
a plurality of test pins, wherein each of the test pills receives test data for a plurality of columns of logic blocks;
a first register comprising a series of flop-flops, a first flip-flop selectively coupled one of the plurality of test pins, wherein test data is loaded into the first register serially via a test pin under control of a first clock signal on a first clock line; and
a second register comprising a plurality of flip-flops, each of the plurality of flip-flops coupled to one of the series of flip-flops in the first register, the second register coupled to a plurality of columns of logic blocks, wherein test data stored in the first register is loaded into the second register in parallel under control of a second clock signal on a second clock line. - View Dependent Claims (29)
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Specification