Interface circuitry

• US 6,538,472 B1
• Filed: 05/02/2001
• Issued: 03/25/2003
• Est. Priority Date: 05/02/2001
• Status: Active Grant

• Current Assignee: SPX Corporation
• Original Assignee: SPX Corporation
• Inventors: McGee, Phillip
• Primary Examiner(s): LE, DON P
• Application Number:
  US09/846,373
• Time in Patent Office: 692 Days
• Field of Search: 701/29, 307/10.1, 326/80, 326/82, 326/89, 326/39
• US Class Current: 326/82
• CPC Class Codes: H03K 19/01825 Coupling arrangements, impedance matching circuits

Abstract

Interface circuitry for linking an automobile diagnostic scanner to the electronic control unit of an automobile. The disclosed circuitry provides a lower cost, reduced board space solution for an universal scan tool interface circuitry.

Claims

1. Interface circuitry for an automobile electronic control unit diagnostic scanner, comprising:

a first resistor;

a second resistor;

a transistor array;

wherein said first resistor is connected at a first end to a collector of a first transistor of the transistor array;

wherein said second resistor is connected at a first end to a collector of a second transistor of the transistor array;

wherein said first and said second resistors are connected at their second ends to a first pin of an link connector; and

wherein a plurality of resistance values can be provided at the first pin of the link connector by biasing a base of the first transistor, the second transistor and a base of both transistors.

2. The interface circuitry of claim 1 further comprising a third resistor connected at a first end to the collector of a third transistor of the transistor array and connected at a second end to the first pin of the link connector.

3. The interface circuitry of claim 2 wherein an emitter of the first and second transistors are tied to ground.

4. The interface circuitry of claim 3 wherein said transistor array is an NPN array.

5. The interface circuitry of claim 4 further comprising a field programmable gate array (FPGA) electrically connected to the bases of the first, second, and third transistors.

6. The interface circuitry of claim 5 further comprising a first, second, and third inverter interposed, respectively, between the FPGA and the first, second, and third transistor.

7. The interface circuitry of claim 6 further comprising a fourth transistor having:

a base connected to the FPGA through an inverter;

an emitter connected to ground; and

a collector connected to a second pin of the link connector through a fourth resistor; and

wherein a first voltage supply is connected to said emitter of said fourth transistor.

8. The interface circuitry of claim 7 further comprising a second voltage source connected to said emitter of said fourth transistor.

9. The interface circuitry of claim 8 further comprising a fifth transistor having a base connected to an input capture pin from said link connector;

and

having a collector connected to said FPGA.

10. The interface circuitry of claim 9, further comprising a voltage clamp circuit connected to the base of said fifth transistor.

11. The interface circuitry of claim 10, wherein said transistor array is a seven segment display driver.

12. The interface circuitry of claim 11, wherein said first resistance is a 10 kilo Ohm resistor and said second resistor is a 39.2 kilo Ohm transistor.

13. The interface circuitry of claim 12 wherein said first voltage source is 5 volts.

14. Interface circuitry for an automobile electronic control unit diagnostic scanner, comprising:

means for providing a plurality of resistances at a first and second pin of a link connector; and

means for selecting the resistance to be provided at the first and second pin of said link connector.

15. The interface circuitry of claim 14 further comprising means for converting signals received at said link connector from an electronic control unit from a first voltage to a second voltage.

16. The interface circuitry of claim 15, wherein said means for providing a plurality of resistances includes an NPN array.

17. A method of accessing trouble codes in an automobile electronic control unit, comprising the steps of:

transmitting an electronic signal from a field programmable gate array;

biasing a transistor of a gate array with said transmitted signal; and

receiving an electronic signal at said gate array representative of a trouble code.

18. The method of claim 17 wherein said gate array is an NPN seven segment display driver array.

19. The method of claim 18 further comprising the step of biasing a second transistor of said gate array to vary the resistance provided to said electronic control unit.

20. The method of claim 19 wherein said step of biasing said second transistor varies the voltage provided to said electronic control unit.