Compensation method in a class-G amplifier output stage

• US 6,538,514 B2
• Filed: 05/22/2002
• Issued: 03/25/2003
• Est. Priority Date: 05/22/2001
• Status: Expired due to Fees

• Current Assignee: Elantec Semiconductor, LLC (Renesas Electronics Corporation)
• Original Assignee: Elantec Semiconductor, LLC (Renesas Electronics Corporation)
• Inventors: Harvey, Barry A.
• Primary Examiner(s): NGUYEN, PATRICIA T
• Application Number:
  US10/153,837
• Publication Number:
  US 20020175760A1
• Time in Patent Office: 307 Days
• Field of Search: 330/263, 330/269, 330/267, 330/268, 330/292, 330/265
• US Class Current: 330/265
• CPC Class Codes: H03F 1/0244 Stepped control
• CPC Class Codes: H03F 1/0255 by using a signal derived from the output signal
• CPC Class Codes: H03F 1/083 in transistor amplifiers H03F1/10 - H03F1/22 take precedence
• CPC Class Codes: H03F 3/3076 with symmetrical driving of the end stage
• CPC Class Codes: H03F 3/4517 Complementary non-cross coupled types

Abstract

An improved class-G amplifier (FIG. 2) is provided by adding a first capacitor (82) between the input of current mirror (18) and node p, and by adding a second capacitor (84) between the input of current mirror (20) and node m. The added capacitors (82) and (84) can be sized to stabilize frequency responses when high power supplies are enabled. The added capacitors (82) and (84) further function to reduce transient currents during switching through the crossover points between first upper and lower power supplies (Vsp1, Vsph) and between second upper and lower power supplies (Vsm1, Vsmh).

Claims

1. An output stage for a Class-G Amplifier comprising:

a first current mirror (18) having an input (I_IN) driven by a first half cycle of an input signal provided to an input of the of the Class-G amplifier, and having an output (I_OUT(Cm−

));

a second current mirror (20) having an input (I_IN) driven by a second half cycle of an input cycle provided to the input of the Class-G amplifier, and having an output (I_OUT(Cm+));

series connected diodes (14) connected between the outputs of the first and second current mirrors (18,20);

a pair of emitter follower transistors (32,34) having common emitters forming an output (output) of the amplifier, a first one of the pair of emitter follower transistors (32) having a base connected to the output (I_OUT(Cm−

) of the first current mirror (18) and a collector forming a node p, and a second one of the pair of emitter follower transistors (34) having a base connected to the output (I_OUT(Cm−

)) of the second current mirror (20) and a collector forming a node m;

a first voltage source (26) having a negative terminal connected to the output of the amplifier, and having a positive terminal;

a second voltage source (28) having a positive terminal connected to the output of the amplifier, and having a negative terminal;

a first low voltage control diode (38) having a first terminal connected to a first low voltage power supply terminal (Vsp1), and a second terminal connected to the node p;

a first high voltage control transistor (30) having a collector-emitter path connecting the node p to the first high power supply terminal (Vsph), and having a base connected to the positive terminal of the first voltage source (26);

a second low voltage control diode (40) having a first terminal connected to a second low voltage power supply terminal (Vsm1), and having a second terminal connected to the node m;

a second high voltage control transistor (36) having a collector-emitter path connecting the node m to the second high power supply terminal (Vsmh), and having a base connected to the negative terminal of the second voltage source (28);

a first compensation capacitor (82) having a first terminal connected to the input of the first current mirror (18) and a second terminal connected to the node p; and

a second compensation capacitor (84) having a first terminal connected to the input of the second current mirror (20) and a second terminal connected to the mode m.

2. A Class-G amplifier comprising:

an input stage for receiving a signal input to the Class-G amplifier and providing a first output and a second output; and

an output stage comprising;

a pair or current mirrors (18,20) comprising a first current mirror (18) receiving the first output of the input stage and having a first current mirror output, and a second current mirror (20) receiving the second output of the input stage and having a second current mirror output;

a pair of diodes (38,40) comprising a first diode (38) connecting a first low voltage supply terminal (Vsp1) to a signal node p providing a first voltage to the output of the Class-G amplifier, and a second diode (40) connecting a second low voltage supply terminal (Vsp1) to a signal node m for providing a second voltage to the output of the Class-G amplifier;

a pair of transistors (32,34) comprising a first transistor (32) connecting a first high voltage supply terminal (Vsph) to the signal node p as controlled by a first voltage offset from the Class-G amplifier output, and a second transistor (34) connecting a second high voltage supply terminal (Vsmh) to the signal node m as controlled by a second voltage offset from the Class-G amplifier output; and

a pair of compensation capacitors (82,84) comprising a first compensation capacitor (82) connecting the first current mirror output to the node p, and a second compensation capacitor (84) connecting the second current mirror output to the node m.

3. The Class-G amplifier of claim 2, wherein the first transistor (32) and the second transistor (34) of the pair of transistors (32,34) comprise CMOS devices.

4. The Class-G amplifier of claim 2, wherein the first transistor (32) and the second transistor (34) of the pair of transistors (32,34) comprise BJT devices.

5. The Class-G amplifier of claim 2, wherein the input stage comprises:

a first transistor (2) having a collector-emitter path connected between a first high voltage power supply terminal (Vsph) and a second high voltage power supply terminal (Vsmh), and having a base forming a first input (+input) of the amplifier;

a second transistor (4) having a collector-emitter path connected between the first high voltage power supply terminal (Vsph) and the second high voltage power supply terminal (Vsmh), and having a base connected to the first input (+input) of the amplifier; and

a first pair of emitter follower transistors (6,8) having common emitters forming a second input (−

input) of the amplifier, and collectors connected between the inputs of the first and second current mirrors (18,20), wherein a base of a first one (8) of the first pair of emitter follower transistors is connected to the emitter of the first transistor (2), while a base of a second one of the first pair of emitter follower transistors (6) is connected to the emitter of the second transistor (4).

6. The Class-G amplifier of claim 5, further comprising:

a feedback resistor (42) connecting the output of the amplifier to the second input (−

input) of the amplifier.

7. The amplifier of claim 5, further comprising:

a first current sink (12) coupling the first high power supply terminal (Vsph) to the emitter of the second transistor; and

a second current sink (10) coupling the second high power supply terminal (Vsmh) to the emitter of the first transistor (12).

8. An amplifier comprising:

a first transistor (2) having a collector-emitter path connected between a first high voltage terminal (Vsph) and a second high voltage terminal (Vsmh), and having a base forming a first input (+input) of the amplifier;

second transistor (4) having a collector-emitter path connected between the first high voltage terminal (Vsph) and the second high voltage terminal (Vsmh), and having a base connected to the first input (+input) of the amplifier;

a first current mirror (18) having an input (I_IN) and an output (I_OUT(Cm−

));

a second current mirror (20) having an input (IN) and an output (I_OUT(Cm+));

a first pair of emitter follower transistors (6,8) having common emitters forming a second input (−

input) of the amplifier, and collectors connected between the inputs of the first and second current mirrors (18,20), wherein a base of a first one of the first pair of emitter follower transistors (8) is connected to the emitter of the first transistor (2), while a base of a second one to of the first pair of emitter follower transistors (6) is connected to the emitter of the second transistor (4);

series connected diodes (14,16) connected between the outputs of the first and second current mirrors (18,20);

a second pair of emitter follower transistors (32,34) having common emitters forming an output (output) of the amplifier, a first one of the second pair of emitter follower transistors having a base connected to the output (I_OUT(Cm−

) of the first current mirror (18) and a collector forming a node p, and a second one of the second pair of emitter follower transistors having a base connected to the output (I_OUT(Cm−

)) of the second current mirror (20) and a collector forming a node m;

a first voltage source (26) having a negative terminal connected to the output of the amplifier, and having a positive terminal;

a second voltage source (28) having a positive terminal connected to the output of the amplifier, and having a negative terminal;

a first low voltage control diode (38) having a first terminal connected to a first low voltage power supply terminal (Vsp1), and a second terminal connected to the node p;

a first high voltage control transistor (30) having a collector-emitter path connecting the node p to the first high voltage power supply terminal (Vsph), and having a base connected to the positive terminal of the first voltage source (26);

a second low voltage control diode (40) having a first terminal connected to a second low voltage power supply terminal (Vsm1), and having a second terminal connected to the node m;

a second high voltage control transistor (36) having a collector-emitter path connecting the node m to the second high power supply terminal (Vsmh), and having a base connected to the negative terminal of the second voltage source (36);

a first compensation capacitor (82) having a first terminal connected to the input of the first current mirror (18) and a second terminal connected to the node p; and

a second compensation capacitor (84) having a first terminal connected to the input of the second current mirror (20) and a second terminal connected to the mode m.

9. The amplifier of claim 8, further comprising:

a feedback resistor (42) connecting the output of the amplifier to the second input (−

input) of the amplifier.

10. The amplifier of claim 9, further comprising:

a first current sink (12) coupling the first high power supply terminal (Vsph) to the emitter of the second transistor; and

a second current sink (10) coupling the second high power supply terminal (Vsmh) to the emitter of the first transistor (12).