Synchronizing conversion apparatus and method as well as recording medium

• US 6,538,700 B1
• Filed: 06/23/2000
• Issued: 03/25/2003
• Est. Priority Date: 06/25/1999
• Status: Expired due to Fees

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Kobayashi, Hiroshi, Ohta, Masashi, Fukuda, Kyoko
• Primary Examiner(s): LEE, MICHAEL
• Application Number:
  US09/602,828
• Time in Patent Office: 1,005 Days
• Field of Search: H04/N.9475, 348/513, 348/512, 348/514, 348/497, 348/571, 348/536, 348/537, 348/565, 348/567, 348/568, 348/714, 348/715, 348/718, 345/564, 345/566, 345/547
• US Class Current: 348/513
• CPC Class Codes: H04N 5/0736 using digital storage buffer techniques
• CPC Class Codes: H04N 5/147 Scene change detection

Abstract

The invention provides a synchronizing conversion apparatus wherein outpacing compensation can be executed with a circuit construction including a comparatively small number of components. A read control circuit produces a read control signal including a read address and a read timing based on an outpacing detection signal from a phase comparison circuit, which is generated taking a time required for processing of a memory access arbitration circuit into consideration, and a scene change detection signal from a scene change detection circuit. The read control signal is outputted to the memory access arbitration circuit. The memory access arbitration circuit arbitrates requests from a write control circuit and the read control circuit to control writing into and reading out from a frame memory.

Claims

1. A synchronizing conversion apparatus for converting a synchronizing frequency of an image signal, comprising:

an image memory;

write means for writing the image signal into said image memory in synchronism with a first synchronizing frequency signal inputted thereto;

read means for reading out the image signal from said image memory in synchronism with a second synchronizing frequency signal inputted to said read means and having a frequency different from that of the first synchronizing frequency signal;

detection means for detecting a phase difference between the first and second synchronizing frequency signals;

prediction means for predicting occurrence of outpacing between a read address and a write address for said image memory based on the phase difference detected by said detection means;

modification means for modifying a reading out timing of said read means in response to a result of the prediction of said prediction means; and

delay compensation means for executing delay compensation for the image signal read out by said read means in response to the result of the prediction of said prediction means.

2. A synchronizing conversion apparatus according to claim 1, wherein said detection means additionally detects a variation of the phase difference which arises from a fluctuation of the frequency of the first or second synchronizing frequency signal.

3. A synchronizing conversion apparatus according to claim 1, further comprising scene change detection means for detecting a scene change of the image signal, and wherein said modification means modifies the reading out timing of said read means in response to a timing at which a scene change of the image signal is detected by said scene change detection means.

4. A synchronizing conversion apparatus according to claim 1, which comprises two or more read systems each of which includes said read means, detection means, prediction means, modification means and delay compensation means.

5. A synchronizing conversion apparatus according to claim 4, further comprising arbitration means for arbitrating the writing process of said write means into said image memory and reading out processes of said read means of said read systems from said image memory.

6. A synchronizing conversion apparatus according to claim 5, wherein said prediction means predicts occurrence of outpacing between the read address and the write address for said image memory based on the phase difference detected by said detection means and a time required for the arbitration process of said arbitration means.

7. A synchronizing conversion apparatus according to claim 5, further comprising delay means for delaying the first and second synchronizing frequency signals by a time required for the arbitration process of said arbitration means and supplying the delayed first and second synchronizing frequency signals to said detection means.

8. A synchronizing conversion method for a synchronizing conversion apparatus for converting a synchronizing frequency of an image signal, comprising:

a write step of writing the image signal into an image memory in synchronism with a first synchronizing frequency signal inputted to said synchronizing conversion apparatus;

a read step of reading out the image signal from said image memory in synchronism with a second synchronizing frequency signal inputted to said synchronizing conversion apparatus and having a frequency different from that of the first synchronizing frequency signal;

a detection step of detecting a phase difference between the first and second synchronizing frequency signals;

a prediction step of predicting occurrence of outpacing between a read address and a write address for said image memory based on the phase difference detected by the detection step;

a modification step of modifying a reading out timing of the read step in response to a result of the prediction of the prediction step; and

a delay compensation step of executing delay compensation for the image signal read out by the read step in response to the result of the prediction of the prediction step.

9. A recording medium on which a computer-readable program for synchronizing conversion for converting a synchronizing frequency of an image signal is recorded, the program comprising:

a write step of writing the image signal into an image memory in synchronism with a first synchronizing frequency signal inputted to said synchronizing conversion apparatus;

a read step of reading out the image signal from said image memory in synchronism with a second synchronizing frequency signal inputted to said synchronizing conversion apparatus and having a frequency different from that of the first synchronizing frequency signal;

a detection step of detecting a phase difference between the first and second synchronizing frequency signals;

a prediction step of predicting occurrence of outpacing between a read address and a write address for said image memory based on the phase difference detected by the detection step;

a modification step of modifying a reading out timing of the read step in response to a result of the prediction of the prediction step; and

a delay compensation step of executing delay compensation for the image signal read out by the read step in response to the result of the prediction of the prediction step.