Semiconductor integrated circuit having test circuit

• US 6,538,936 B2
• Filed: 06/25/2001
• Issued: 03/25/2003
• Est. Priority Date: 12/25/2000
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Tanaka, Koji, Hayakawa, Goro
• Primary Examiner(s): Lebentritt, Michael S.
• Assistant Examiner(s): PHUNG, ANH K
• Application Number:
  US09/887,167
• Publication Number:
  US 20020080667A1
• Time in Patent Office: 638 Days
• Field of Search: 365/201, 365/204, 365/226, 365/149, 365/189.09, 327/536, 327/537, 327/589, 327/437, 307/110
• US Class Current: 365/201
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters

Abstract

A pump circuit forming a boosted power supply (Vpp) generating circuit includes: first and second pumps generating a boosted power supply; and a test circuit controlling levels of stress applied to the first and second pumps in accordance with a signal input from a ring oscillator and a test signal. A semiconductor memory device of the present invention enables application of a desired level of stress to each capacitor of the pump circuit formed for a stress test, and provides enhanced efficiency of the stress test and increased reliability of the semiconductor integrated circuit.

Claims

1. A semiconductor integrated circuit, comprising:

a memory cell array region including a plurality of memory cells arranged in rows and columns, a plurality of word lines arranged corresponding to said rows, and a plurality of bit lines arranged corresponding to said columns;

a plurality of capacitors for generating a boosted voltage supplied to said memory cell array region; and

a test circuit -controlling levels of stress applied to said plurality of capacitors.

2. The semiconductor integrated circuit according to claim 1, wherein said test circuit is controlled by a test signal.

3. The semiconductor integrated circuit according to claim 1, wherein said test circuit applies a predetermined voltage difference between electrodes of each of at least one of said plurality of capacitors in a test operation.

4. The semiconductor integrated circuit according to claim 2, wherein said test circuit controls the levels of stress applied to said plurality of capacitors in accordance with said test signal.

5. The semiconductor integrated circuit according to claim 2, wherein said test circuit simultaneously controls the levels of stress applied to said plurality of capacitors in accordance with said test signal.

6. The semiconductor integrated circuit according to claim 2, wherein said test signal is input from an external signal pin.

7. The semiconductor integrated circuit according to claim 2, wherein said test signal is input from an external pad.

8. The semiconductor integrated circuit according to claim 2, further comprising a test signal generating circuit internally generating said test signal.

9. The semiconductor integrated circuit according to claim 7, wherein said test signal generating circuit generates said test signal in accordance with an input from an external signal pin.

10. The semiconductor integrated circuit according to claim 7, wherein said test signal generating circuit generates said test signal in accordance with an input from an external pad.