Semiconductor integrated circuit for which high voltage countermeasure was taken

• US 6,538,955 B2
• Filed: 07/17/2001
• Issued: 03/25/2003
• Est. Priority Date: 08/29/2000
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Kohno, Fumihiro
• Primary Examiner(s): Ho, Hoai
• Application Number:
  US09/906,116
• Publication Number:
  US 20020024876A1
• Time in Patent Office: 616 Days
• Field of Search: 365/230.6, 365/230.01, 326/105
• US Class Current: 365/230.06
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

There are provided a plurality of CMOS configured pre-driver circuits, wherein an increased voltage obtained by increasing a power voltage is applied to a source of each P-channel transistor, and a word line driver circuit each having a P-channel transistor and an N-channel transistor to which an output of the pre-driver circuit is inputted. The source of each N-channel transistor in the plurality of pre-driver circuits is connected in common to that of each N-channel transistor in the word line driver circuit, and a source-drain path of an N-channel transistor for voltage alleviation is connected between this source common node and a node of a grounding voltage. The increased voltage is applied to a gate of the N-channel transistor for voltage alleviation.

Claims

1. A semiconductor integrated circuit comprising:

a first node to which a first voltage is applied;

a plurality of first transistors of a first channel each having a current path which has a first end and a second end and a gate, the first end of the current path being connected to the first node;

a plurality of second nodes to which the second end of the current paths of the plurality of the first transistors is connected, respectively;

a plurality of second transistors of a second channel each having a current path which has a first end and a second end and a gate, the first end of the current path is connected to one of the second nodes, respectively;

a third node to which the second ends of the current paths of the plurality of second transistors are connected in common;

a fourth node to which a second voltage lower than the first voltage is applied;

a third transistor of the second channel having a current path and a gate, the current path is connected between the third node and the fourth node, and a third voltage higher than the second voltage is applied to the gate; and

wherein the first, second, and third voltages are constant voltages.

2. The semiconductor integrated circuit according to claim 1, wherein the first channel is a P-channel, and the second channel is an N-channel.

3. The semiconductor integrated circuit according to claim 1, wherein the first voltage is an increased voltage obtained by increasing a power voltage.

4. The semiconductor integrated circuit according to claim 1, wherein the third voltage is a voltage equal to the first voltage.

5. The semiconductor integrated circuit according to claim 3, wherein the third voltage is a voltage equal to the power voltage.

6. The semiconductor integrated circuit according to claim 1, wherein a signal produced by decoding a plurality of address signals is supplied to at least one gate of the plurality of the first or second transistors.

7. The semiconductor integrated circuit according to claim 1, wherein the second voltage is a negative voltage.

8. A semiconductor integrated circuit comprising:

a first node to which a first voltage obtained by increasing a power voltage is applied;

a plurality of decode circuits arranged in an array, the plurality of decode circuits each comprising;

a partial decode circuit for decoding address signals;

pre-driver circuits each having at least one inverter circuit which comprises a first transistor of a P-channel having a source, a drain, and a gate, the source being connected to the first node, and a second transistor of an N-channel having a source, a drain and a gate, the drain of the second transistor being connected to a drain of the first transistor, an output of the partial decode circuit being inputted to the gate of each of the first and second transistors; and

a word line driver circuit comprises a third transistor of a P-channel having a source, a drain and a gate, the source of the third transistor being connected to the first node, and a fourth transistor of an N-channel having a source, a drain, and a gate, the drain of the fourth transistor being connected to a drain of the third transistor, and the source of the fourth transistor being connected to a source of the second transistor, an output of the pre-driver circuit being supplied to the word line drive circuit;

a second node to which a second voltage lower than the first voltage is applied;

a fifth transistor of an N-channel having a source, a drain, and a gate, a source-drain path is connected between a common source connection node of the second and fourth transistors and the second node, and a third voltage higher than the second voltage is applied to the gate;

wherein the first, second, and third voltages are constant voltages.

9. The semiconductor integrated circuit according to claim 8, wherein the first voltage is an increased voltage obtained by increasing a power voltage.

10. The semiconductor integrated circuit according to claim 8, wherein the third voltage is a voltage equal to the first voltage.

11. The semiconductor integrated circuit according to claim 9, wherein the third voltage is a voltage equal to the power voltage.

12. The semiconductor integrated circuit according to claim 8, wherein the second voltage is a negative voltage.

13. The semiconductor integrated circuit according to claim 8, wherein the fifth transistor is arranged at a position different from the plurality of decode circuits arranged in the array.

14. The semiconductor integrated circuit according to claim 8, wherein the fifth transistor is disposed on each of decode circuits arranged in the array.