Delay locked loop circuitry for clock delay adjustment

• US 6,539,072 B1
• Filed: 03/13/2000
• Issued: 03/25/2003
• Est. Priority Date: 02/06/1997
• Status: Expired due to Term

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Garlepp, Bruno W., Horowitz, Mark A., Chan, Yiu-Fai, Tran, Chanh Vi, Kim, Jun, Lee, Thomas H., Stark, Donald C., Johnson, Mark G., Lau, Benedict C., Donnelly, Kevin S., Yu, Leung, Chau, Pak Shing, Nguyen, Nhat M.
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): Fan, Chieh M.
• Application Number:
  US09/524,402
• Time in Patent Office: 1,107 Days
• Field of Search: 375/358, 375/371, 375/373, 375/375, 375/376, 327/141, 327/5, 327/163, 327/261, 327/276, 331/14, 331/17, 331/25
• US Class Current: 375/371
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: H03K 2005/00026 controlled by an analog electrical signal, e.g. obtained after conversion by a D/A converter
• CPC Class Codes: H03K 2005/00032 Dc control of switching transistors
• CPC Class Codes: H03K 2005/00052 by mixing the outputs of fixed delayed signals with each other or with the input signal
• CPC Class Codes: H03K 2005/00208 using differential stages
• CPC Class Codes: H03K 5/133 using a chain of active delay devices
• CPC Class Codes: H03K 5/2481 with at least one differential stage
• CPC Class Codes: H03L 7/07 using several loops, e.g. for redundant clock signal generation
• CPC Class Codes: H03L 7/0805 the loop being adapted to provide an additional control signal for use outside the loop
• CPC Class Codes: H03L 7/0814 the phase shifting device being digitally controlled
• CPC Class Codes: H03L 7/0816 the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines
• CPC Class Codes: H04L 7/0025 interpolation of clock signal
• CPC Class Codes: H04L 7/0037 Delay of clock signal

Abstract

Delay locked loop circuitry for generating a predetermined phase relationship between a pair of clocks. A first delay-locked loop includes a delay elements arranged in a chain, the chain receiving an input clock and generating, from each delay element, a set of phase vectors, each shifted a unit delay from the adjacent vector. The first delay-locked loop adjusts the unit delays in the delay chain using a delay adjustment signal so that the phase vectors span a predetermined phase shift of the input clock. A second delay-locked loop selects, from the first delay-locked loop, a pair of phase vectors which brackets the phase of an input clock. A phase interpolator receives the selected pair of vectors and generates an output clock and a delayed output clock, the amount of the delay being controlled by the delay adjustment signal of the first delay-locked loop circuitry. A phase detector compares the delayed output clock with the input clock and adjusts the phase interpolator, based on the phase comparison, so that the phase of the delayed output clock is in phase with the input clock. As a result, there is a predetermined phase relationship between the output clock and the input clock, the phase relationship being the amount of delay between the output clock and the delayed output clock. Different phase relationships between the input and output clock are possible depending on the number of unit delays used in the path of the delayed output clock or the output clock.

Claims

1. A clock alignment circuit, comprising:

a first adjustable delay circuit having a plurality of delay elements to output a plurality of clock signals, each clock signal having a delay time with respect to a reference clock signal, and a respective phase controlled by a delay adjustment signal;

first detector circuitry coupled to the first adjustable delay circuit to compare a phase of a first clock signal of the plurality of clock signals with a phase of the reference clock signal, and to output phase differential information which is representative of a phase differential between the first clock signal and the reference clock signal;

a first control circuit coupled to the first detector circuitry to output the delay adjustment signal, wherein the delay adjustment signal is representative of the phase differential information of the first detector circuitry;

interpolator circuitry to generate a second clock signal using a pair of clock signals of the plurality of clock signals, wherein a phase of the second clock signal is interpolated from respective phases of the pair of clock signals in response to a phase adjustment signal;

a second adjustable delay circuit to output a third clock signal having a delay time with respect to the second clock signal, wherein the delay time of the third clock signal is responsive to the delay adjustment signal;

second detector circuitry coupled to the second adjustable delay circuit to compare the phase of the third clock signal with the phase of an input clock signal, and to output phase differential information which is representative of a phase differential between the third clock signal and the input clock signal; and

a second control circuit coupled to the second detector circuitry to output the phase adjustment signal, wherein the phase adjustment signal is representative of the phase differential information of the second detector circuitry.

2. The clock alignment circuit of claim 1 further comprising selection circuitry to receive the plurality of clock signals and output the pair of clock signals.

3. The clock alignment circuit of claim 2 wherein the selection circuitry comprises a multiplexer coupled to the second detector circuitry to select the pair of clock signals in accordance with the phase differential information of the second detector circuitry.

4. The clock alignment circuit of claim 3 wherein the second control circuitry generates a plurality of selection signals in response to the phase differential information of the second detector circuitry and wherein the multiplexer receives the plurality of selection signals.

5. The clock alignment circuit of claim 1 wherein the second control circuit comprises a counter control circuit and a digital-to-analog converter.

9. The clock alignment circuit of claim 1 wherein a first delay element of the plurality of delay elements comprises:

a fixed delay element having a current source coupled to a pair of differential input transistors; and

an interpolator coupled to the fixed delay element, the interpolator having a first and a second pair of differential input transistors coupled to respective variable current sources.

10. The clock alignment circuit of claim 9 wherein a first variable current source of the respective variable current sources responds to the delay adjustment signal.

11. The clock alignment circuit of claim 1 wherein a first delay element of the plurality of delay elements comprises:

a current source;

a first differential input transistor having a source terminal coupled to the current source, and a drain terminal coupled to a first output terminal;

a second differential input transistor having a source terminal coupled to the current source, and a drain terminal coupled to a second output terminal; and

a first transistor coupled between the first and second output terminals, to limit the voltage swing at one of the first and second output terminals.

12. The clock alignment circuit of claim 1 wherein the interpolation circuitry comprises:

a first pair of differential input transistors coupled to a first variable current source, wherein the first pair of differential input transistors are coupled to a first pair of clock signals of the plurality of clock signals and the first variable current source is responsive to the phase adjustment signal; and

a second pair of differential input transistors coupled to a second variable current source, wherein the second pair of differential input transistors are coupled to a second pair of clock signals of the plurality of clock signals and the second variable current source is responsive to the phase adjustment signal.

13. The clock alignment circuit of claim 1 further including a third adjustable delay circuit to output a fourth clock signal having a delay time with respect to the second clock signal, the delay time of the fourth clock signal being responsive to the delay adjustment signal.

14. The clock alignment circuit of claim 1 further comprising a duty cycle correction circuit coupled to the first adjustable delay circuit to receive the reference clock signal.

6. The clock alignment circuit of 5, wherein the digital-to-analog converter comprises:

a plurality of first switches; and

a plurality of current sources, each current source coupled in series with one of the plurality of first switches.

7. The clock alignment circuit of claim 6 wherein the counter control circuit generates a digital count value representative of the phase differential between the third clock signal and the input clock signal, and wherein the digital-to-analog converter couples at least one current source of the plurality of current sources to an output terminal in response to the digital count value.

8. The clock alignment circuit of claim 6 wherein the digital-to-analog converter further includes a plurality of second switches coupled to receive a second digital count value, wherein the second digital count value is complementary to the first digital count value, and wherein each current source is coupled in series with one of each of the plurality of second switches.

15. A clock alignment circuit, comprising:

a first delay lock loop including;

an adjustable delay circuit having a plurality of delay elements to output a plurality of clock signals, each clock signal having a delay time with respect to a reference clock signal, and a respective phase which is responsive to a delay adjustment signal;

detector circuitry coupled to the first adjustable delay circuit to compare a phase of a first clock signal of the plurality of clock signals with a phase of the reference clock signal, and to output phase differential information which is representative of a phase differential between the first clock signal and the reference clock signal; and

a second delay lock loop including;

an adjustable delay circuit to output a third clock signal having a delay time with respect to a second clock signal, the delay time of the third clock signal being responsive to the delay adjustment signal; and

detector circuitry coupled to the adjustable delay circuit to compare the phase of the third clock signal with the phase of an input clock signal, and to control a phase of the second clock using the plurality of clock signals in accordance with a phase differential between the third clock signal and the input clock signal.

16. The clock alignment circuit of claim 15 further comprising a multiplexer coupled to the detector circuitry of the second delay lock loop to select a pair of clock signals of the plurality of clock signals.

17. The clock alignment circuit of claim 16 wherein the detector circuitry of the second delay lock loop generates a plurality of selection signals in response to the phase differential between the third clock and the input clock signal, and wherein the multiplexer receives the plurality of selection signals.

18. The clock alignment circuit of claim 15 further comprising interpolator circuitry to generate the second clock signal using a pair of clock signals of the plurality of clock signals, the phase of the second clock signal being interpolated from respective phases of the pair of clock signals in accordance with the phase differential between the third clock signal and the input clock signal.

19. The clock alignment circuit of claim 18 wherein the interpolation circuitry comprises:

a first pair of differential input transistors coupled to a first variable current source, wherein the first pair of differential input transistors are coupled to a first pair of clock signals of the plurality of clock signals; and

a second pair of differential input transistors coupled to a second variable current source, wherein the second pair of differential input transistors are coupled to a second pair of clock signals of the plurality of clock signals.

21. The clock alignment circuit of claim 15 further comprising:

a counter control circuit to generate a first and second digital count value, wherein the first and second digital count values are complementary and representative of the phase differential between the third clock signal and the input clock signal;

a plurality of current sources;

a first plurality of switches coupled between the plurality of current sources and a first output terminal, the first plurality of current sources being responsive to the first digital count value, to couple corresponding current sources to the first output terminal; and

a second plurality of switches coupled between the plurality of current sources and a second output terminal, the second plurality of switches being responsive to the second digital count value, to couple corresponding current sources to the second output terminal.

22. The clock alignment circuit of claim 15 wherein a first delay element of the plurality of delay elements comprises:

a fixed delay element having a current source coupled to a pair of differential input transistors; and

an interpolator coupled to the fixed delay element, the interpolator having a first and a second pair of differential input transistors coupled to respective variable current sources.

23. The clock alignment circuit of claim 15 wherein a first delay element of the plurality of delay elements comprises:

a current source;

a first differential input transistor having a source terminal coupled to the current source, and a drain terminal coupled to a first output terminal;

a second differential input transistor having a source terminal coupled to the current source, and a drain terminal coupled to a second output terminal; and

a first transistor coupled between the first and second output terminals, to limit the voltage swing at one of the first and second output terminals.

20. The clock alignment circuit of 15 further comprising:

a counter control circuit to generate a first digital count value representative of the phase differential between the third clock signal and the input clock signal; and

a digital-to-analog converter coupled to the counter control circuit, the digital-to-analog converter including a plurality of current sources and respective first switches, each current source coupled in series between with one of each respective first switch.

24. A clock alignment circuit, comprising:

a first adjustable delay circuit having a plurality of delay elements to output a plurality of clock signals, each clock signal having a delay time with respect to a reference clock signal, and a respective phase which is controlled by a delay adjustment signal;

first detector circuitry coupled to the first adjustable delay circuit to compare a phase of a first clock signal of the plurality of clock signals with a phase of the reference clock signal, and to output a phase differential information which is representative of a phase differential between the first clock signal and the reference clock signal;

a first control circuit including a counter circuit and a digital-to-analog converter, wherein the first control circuit is coupled to the first detector circuitry to output the delay adjustment signal, wherein the delay adjustment signal is representative of the phase differential information of the first detector circuitry;

a second adjustable delay circuit to output a third clock signal having a delay time with respect to a second clock signal, the delay time of the third clock signal being responsive to the delay adjustment signal; and

interpolator circuitry to generate the second clock signal using a pair of clock signals of the plurality of clock signals, a phase of the second clock signal being interpolated from respective phases of the pair of clock signals.

25. The clock alignment circuit of claim 24 wherein a first delay element of the plurality of delay elements comprises:

a fixed delay element having a current source coupled to a pair of differential input transistors; and

an interpolator coupled to the fixed delay element, the interpolator having a first and a second pair of differential input transistors coupled to respective variable current sources.

26. The clock alignment circuit of claim 24 wherein a first delay element of the plurality of delay elements comprises:

a current source;

a first differential input transistor having a source terminal coupled to the current source, and a drain terminal coupled to a first output terminal;

a second differential input transistor having a source terminal coupled to the current source, and a drain terminal coupled to a second output terminal; and

a first transistor coupled between the first and second output terminals, to limit the voltage swing at one of the first and second output terminals.

27. The clock alignment circuit of claim 24 further comprising second detector circuitry coupled to the second adjustable delay circuit to compare the phase of the third clock signal with the phase of an input clock signal, and to control the phase of the second clock using the plurality of clock signals in accordance with a phase differential between the third clock signal and the input clock signal.

28. The clock alignment circuit of claim 27 wherein the second detector circuitry comprises a second control circuit including a counter circuit and a digital-to-analog converter.

29. The clock alignment circuit of claim 27 wherein the second detector circuitry comprises a multiplexer to select a pair of clock signals of the plurality of clock signals.

30. The clock alignment circuit of claim 29 wherein the second detector circuitry generates a plurality of selection signals that represent the phase difference between the third clock signal and the input clock signal, and wherein the multiplexer receives the plurality of selection signals.

31. The clock alignment circuit of claim 24 wherein the interpolator circuitry comprises:

a first pair of differential input transistors coupled to a first variable current source, wherein the first pair of differential input transistors receives a first phase of the pair of clock signals and the first variable current source; and

a second pair of differential input transistors coupled to a second variable current source, wherein the second pair of differential input transistors receives a second phase of the pair of clock signals and the second variable current source.