System and method for control synthesis using a reachable states look-up table

• US 6,539,477 B1
• Filed: 03/03/2000
• Issued: 03/25/2003
• Est. Priority Date: 03/03/2000
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Chameleon Systems, Inc.
• Inventors: Seawright, J. Andrew
• Primary Examiner(s): BUTLER, DENNIS
• Application Number:
  US09/518,553
• Time in Patent Office: 1,117 Days
• Field of Search: 713/1, 713/100, 708/232
• US Class Current: 713/100
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

Abstract

A system and method of implementing thereof that maps and condenses system control using reachable state control words is described. The system includes a control logic block, a look-up table which stores N-bit reachable state control words derived from an implementation description N-bit control signal, and a logic hardware block. The control logic block accesses the look-up table with a M-bit control word address. The accessed look-up table outputs a N-bit reachable state control word which is used to control the logic hardware block so as to simulate functions as defined by a user input description. A method for implementing the system is performed by synthesizing the user input description to generate an implementation description which describes a control model of the system in terms of a control logic block driving a logic hardware block with a N-bit control signal. The implementation description is analyzed to determine the reachable states of the N-bit control signal. A look-up table is created by storing N-bit reachable state control words corresponding to each reachable state of the N-bit control signal. A mapping function is determined between each reachable state control word stored in the look-up table and a M-bit control word address for accessing the look-up table. Finally, a control logic block is configured or programmed to implement the determined mapping function.

Claims

1. A method of implementing a system defined by a user input description, said system having a control logic block and a logic hardware block, said method comprising the steps of:

synthesizing said user input description so as to generate an implementation description which includes a description of a control model of said system in which a control model control logic block drives a control model logic hardware block with a N-bit control signal;

analyzing said implementation description to determine reachable states of said N-bit control signal;

creating a look-up table by storing a N-bit reachable state control word corresponding to each of said reachable states in a digital storage area, each N-bit reachable state control word being accessible by a corresponding M-bit address, wherein M<

N;

configuring said control logic block by;

a) determining a mapping function between said reachable state control words and M-bit control word addresses for accessing said look-up table and;

b) implementing said mapping function in said control logic block.

2. The method as described in claim 1 wherein said step of implementing said mapping function is performed by programming said control logic block with a set of configuration bits causing said control logic block to perform said mapping function.

3. The method as described in claim 2 further comprising the step of storing said set of configuration bits in a configuration data memory.

4. The method as described in claim 1 wherein said logic hardware block comprises a plurality of programmable datapath units (DPUs) each having N input ports and wherein said step of analyzing said implementation description further comprises the step of analyzing said implementation description so as to group and assign hardware elements called out in said implementation description to specific ones of said DPUs and determining reachable states of said N-bit control signal corresponding to said each DPU.

5. The system as described in claim 4 wherein said step of creating a look-up table further comprising the step of creating a separate look-up table storing N-bit reachable state control words corresponding to said each DPU.

6. The method as described in claim 1 wherein said step of analyzing said implementation description comprises the step of defining a single function representing said reachable states based on a binary decision diagram.

7. The method as described in claim 1 wherein said step of determining said mapping function comprises the step of using Quine McCluskey logic function minimization of said mapping function by evaluating on-set and off-set conditions of said address and said reachable states.

8. The method as described in claim 1 wherein said user input description is described in terms of a hardware description language (HDL).

9. The method as described in claim 8 wherein said hardware description language (HDL) is Verilog description language.

10. The method as described in claim 1 wherein said user input description is described in terms of a higher level programming language.

11. The method as described in claim 10 wherein said higher level programming language is C programming language.

12. A system having an associated user input description synthesized to generate an implementation description, said implementation description including a description of a control model of said system in which a control model control logic block drives a control model logic hardware block with a N-bit control signal, said system comprising:

a digital storage memory look-up table having M or less N-bit control words corresponding to predetermined reachable states of said N-bit control signal, each N-bit control word having an associated M-bit address for accessing said look-up table, where M<

N;

a control logic block being programmed to perform a mapping function between said predetermined reachable states and said M-bit addresses;

a logic hardware block being driven by accessed N-bit control words from said look-up table to perform functions as defined by said user input description.

13. The system as described in claim 12 wherein said mapping function is a minimized mapping function.

14. The system as described in claim 12 wherein said control logic block is reprogrammable and said control logic block is programmed with a set of configuration bits to perform said mapping function.

15. The system as described in claim 14 further comprising a configuration data memory for storing said set of configuration bits.

16. A reconfigurable system having an associated user input description synthesized to generate an implementation description, said implementation description including a description of a control model of said reconfigurable system in which a reconfigurable control model control logic block drives a reconfigurable control model logic hardware block with a plurality of N-bit control signals, each N-bit control signal for driving a control model datapath unit with said control model logic hardware block, said system comprising:

a plurality of digital storage memory look-up tables each having M or less, N-bit control words corresponding to predetermined reachable states of each of said N-bit control signals, each N-bit control word having an associated M-bit address for accessing said N-bit control word in its corresponding look-up table, where M<

N;

a plurality of reconfigurable datapath units each having N input signal inputs and each corresponding to one of said plurality of look-up tables, wherein in response to an accessed N-bit control word from its said corresponding look-up table each of said datapath units is controlled to perform functions associated with grouped hardware elements called out within said implementation description;

a reconfigurable control logic block programmed to perform a plurality of mapping functions, each of said mapping functions mapping a function between said N-bit control words stored in said one of said look-up tables and said M-bit addresses for accessing said one digital look-up table.

17. The system as described in claim 16 wherein said mapping function is a minimized mapping function.

18. The system as described in claim 17 wherein said reconfigurable control logic block is programmed with a set of configuration bits to perform said mapping function.

19. The system as described in claim 18 further comprising a configuration data memory for storing said set of configuration bits.