Configurable power distribution circuit

• US 6,539,484 B1
• Filed: 12/18/1997
• Issued: 03/25/2003
• Est. Priority Date: 12/18/1997
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Cruz, Claude A.
• Primary Examiner(s): Sheikh, Ayaz
• Assistant Examiner(s): Jean, Frantz B.
• Application Number:
  US08/993,598
• Time in Patent Office: 1,923 Days
• Field of Search: 713/300, 710/107, 714/14, 320/6, 371/22.4, 361/391, 307/454, 370/276
• US Class Current: 713/300
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C

Abstract

Briefly, in accordance with one embodiment of the invention, a circuit includes: a physical arrangement of power transistors. The circuit is adapted to couple a node to a power bus segment. The physical arrangement of power transistors is electronically configurable, based on externally derived electrical signals, to sink power to the node from the power bus segment, source power from the node to the power bus segment, and distribute power through the node.

Claims

1. A circuit comprising:

a physical arrangement of power transistors;

said circuit being adapted to couple a node to a power bus segment;

said physical arrangement of power transistors being electronically configurable, based on externally derived electrical signals, to sink power to the node from the power bus segment, source power from the node to the power bus segment, and distribute power through the node;

wherein said arrangement of transistors is also electronically configurable so that at least two power bus segments are capable of being coupled to the node and electronically isolated from each other at the node.

2. The circuit of claim 1, wherein said transistors comprise power field effect transistors (FETs).

3. The circuit of claim 1, wherein said circuit is coupled to a bus for transferring signals compliant with the 1394 specification.

4. The circuit of claim 1, wherein said node comprises at least a physical layer and a link layer.

5. The circuit of claim 1, wherein said physical arrangement of power transistors is embodied on an integrated circuit (IC) chip.

6. A circuit comprising:

a physical arrangement of power transistors;

said circuit being adapted to couple a node to a power bus segment;

said physical arrangement of power transistors being electronically configurable, based on externally derived electrical signals, to sink power to the node from the power bus segment, source power from the node to the power bus segment, and distribute power through the node;

wherein the power bus segment comprises a power bus segment via which nodes with a particular set of power sink/source relationships may be coupled, and said particular set of power sink/source relationships is time-varying.

7. A method for distributing power among a plurality of nodes via a power bus, comprising:

electronically isolating portions of the power bus into at least two power bus segments; and

configuring particular sets of power sink/source relationships among the nodes coupled to the respective power bus segments of said at least two power bus segments;

wherein the configuring of particular sets of power sink/source relationships among the nodes comprises configuring time-varying power sink/source relationships among the nodes.

8. The method of claim 7, wherein said nodes each comprise at least a physical layer and a link layer.

9. The method of claim 7, wherein the nodes are also coupled by a bus comprising a bus for transferring signals compliant with the 1394 specification.

10. The method of claim 7, wherein configuring particular sets of power sink/source relationships among the nodes comprises applying externally derived electrical signals to an electrically configurable physical arrangement of power transistors.

11. A method for distributing power among a plurality of nodes via a power bus coupling a plurality of nodes together, comprising:

configuring at least one particular set of power sink/source relationships among the nodes coupled via the power bus;

wherein the configuring at least one particular set of power sink/source relationships comprises configuring another particular set of power source/sink relationships other than the at least one particular set of power source/sink relationships, and the at least one particular set of power source/sink relationships and the another particular set of power source/sink relationships are electrically isolated and form two power bus segments.