Apparatus, method and system for synchronizing slave system operations to master system clocking signals in a master-slave asynchronous communication system

• US 6,539,489 B1
• Filed: 03/31/2000
• Issued: 03/25/2003
• Est. Priority Date: 03/31/2000
• Status: Expired due to Term

• Current Assignee: Liberty Patents LLC
• Original Assignee: Siemens AG
• Inventors: Reinert, Matthias
• Primary Examiner(s): Heckler, Thomas M.
• Application Number:
  US09/539,693
• Time in Patent Office: 1,089 Days
• Field of Search: 713/400, 709/248
• US Class Current: 713/400
• CPC Class Codes: G06F 1/14 Time supervision arrangements, e.g. real time clock
• CPC Class Codes: H04J 3/0685 Clock or time synchronisation in a node; Intranode synchronisation

Abstract

A method for synchronizing a slave system and a master system, the method including the steps of providing a slave clock signal based on a communicated master clock signal, providing a time frame in the slave system, wherein the time frame is defined by a minimum time and a maximum time, and a phase of the slave clock signal corresponds to an actual time, determining if the slave clock signal is in the time frame, and regulating the slave clock signal, if it is not in the time frame, so that the slave clock signal occurs within the time frame.

Claims

1. A method for synchronizing a slave system and a master system, the method comprising the steps of:

providing a slave clock signal based on a communicated master clock signal;

providing a time frame in the slave system, wherein the time frame is defined by a minimum time and a maximum time, and a phase of the slave clock signal corresponds to an actual time;

determining if the slave clock signal is in the time frame; and

regulating the slave clock signal, if it is not in the time frame, so that the slave clock signal occurs within the time frame.

2. The method of claim 1, wherein the step of regulating includes the step of phase shifting the slave clock signal so that it occurs after the minimum time and before the maximum time.

3. The method of claim 2, wherein the determining step includes the step of determining whether the actual time is no greater than the minimum time, if the slave clock signal is not in the time frame, and wherein the regulating step includes the step of phase shifting the slave clock signal in one direction, if the actual time is no greater than the minimum time, and phase shifting the slave clock signal in another direction, if the actual time is greater.

4. The method of claim 1, wherein the slave clock signal is a slave clock pulse.

5. The method of claim 1, further comprising the steps of:

providing a master clock signal; and

communicating the master clock signal to the slave system so as to provide the communicated master clock signal.

6. The method of claim 5, further comprising the step of providing another master clock signal, wherein the step of providing the master clock signal is based on the another master clock signal.

7. The method of claim 5, further comprising the step of providing a master event start signal based on the master clock signal.

8. The method of claim 7, further comprising the step of phase compensating the master event start signal based on at least one of a communication delay, a system delay and the time frame.

9. The method of claim 7, wherein the master event start signal is a master event start pulse.

10. A method for synchronizing a slave system and a master system, the method comprising the steps of:

providing a master clock signal in the master system;

communicating the master clock signal to the slave system so as to provide a communicated master clock signal;

providing a time frame in the slave system, wherein the time frame is defined by a minimum time and a maximum time;

providing a slave clock signal based on the communicated master clock signal, wherein a phase of the slave clock signal corresponds to an actual time;

determining if the slave clock signal is in the time frame;

determining if the actual time is no greater than the minimum time, if the slave clock signal is not in the time frame; and

regulating the slave clock signal, if it is not in the time frame, by phase shifting the slave clock signal so that it occurs after the minimum time and before the maximum time in the time frame.

11. The method of claim 10, wherein the slave clock signal is phase shifted in one direction, if the actual time is no greater than the minimum time, and is phase shifted in another direction if the actual time is greater.

12. The method of claim 10, wherein the slave clock signal is a slave clock pulse.

13. The method of claim 10, further comprising the step of providing another master clock signal, wherein the step of providing the master clock signal is based on the another master clock signal.

14. The method of claim 10, further comprising the step of providing a master event start signal based on the master clock signal.

15. The method of claim 14, wherein the master event start signal is phase compensated based on at least one of a communication delay, a system delay and the time frame.

16. The method of claim 14, wherein the master event start signal is a master event start pulse.

17. A system for synchronizing a slave system and a master system, the synchronizing system comprising:

a first generator that generates a time frame, wherein the time frame is defined by a minimum time and a maximum time;

a second generator that generates a slave clock signal based on a communicated master clock signal, wherein a phase of the slave clock signal corresponds to an actual time;

a processor that determines if the slave clock signal is in the time frame; and

a regulator that regulates the slave clock signal, if it is not in the time frame, so that the slave clock signal occurs within the time frame.

18. The system of claim 17, wherein the regulator phase shifts the slave clock signal so that it occurs after the minimum time and before the maximum time.

19. The system of claim 18, wherein the processor determines whether the actual time is no greater than the minimum time, if the slave clock signal is not in the time frame, and wherein the regulator phase shifts the slave clock signal in one direction, if the actual time is no greater than the minimum time, and phase shifts the slave clock signal in another direction, if the actual time is greater.

20. The system of claim 17, wherein the slave clock signal is a slave clock pulse.

21. The system of claim 17, further comprising a third generator that generates a master clock signal, and a communicating apparatus that is adapted to communicate the master clock signal to the slave system so as to provide the communicated master clock signal.

22. The system of claim 21, further comprising a fourth generator that generates another master clock signal, wherein the master clock signal is based on the another master clock signal.

23. The system of claim 21, further comprising a fifth generator that generates a master event start signal based on the master clock signal.

24. The system of claim 23, wherein the fifth generator phase compensates the master event start signal based on at least one of a communication delay, a system delay and the time frame.

25. The system of claim 24, wherein the master event start signal is a master event start pulse.

26. A system for synchronizing a slave system and a master system, the synchronizing system comprising:

means for providing a slave clock signal based on a communicated master clock signal, wherein a phase of the slave clock signal corresponds to an actual time;

means for providing a time frame, wherein the time frame is defined by a minimum time and a maximum time;

means for determining if the slave clock signal is in the time frame; and

means for regulating the slave clock signal, if it is not in the time frame, so that the slave clock signal occurs within the time frame.

27. The system of claim 26, wherein the means for regulating regulates a slave reference clock so that the slave clock signal occurs within the time frame.

28. The system of claim 27, wherein the means for regulating also phase shifts the slave clock signal so that it occurs after the minimum time and before the maximum time.

29. The system of claim 28, wherein the means for determining determines whether the actual time is no greater than the minimum time, if the slave clock signal is not in the time frame, and wherein the means for regulating phase shifts the slave clock signal in one direction, if the actual time is no greater than the minimum time, and phase shifts the slave clock signal in another direction, if the actual time is greater.

30. The system of claim 26, wherein the slave clock signal is a slave clock pulse.

31. The system of claim 26, further comprising means for providing a master clock signal, and means for communicating the master clock signal to the slave system so as to provide the communicated master clock signal.

32. The system of claim 31, further comprising means for generating another master clock signal, wherein the master clock signal is based on the another master clock signal.

33. The system of claim 31, further comprising means for generating a master event start signal based on the master clock signal.

34. The system of claim 33, wherein the means for generating a master event start signal also phase compensates the master event start signal based on at least one of a communication delay, a system delay and the time frame.

35. The system of claim 34, wherein the master event start signal is a master event start pulse.

36. A system for synchronizing a slave system and a master system, the system comprising:

a first generator that generates a master clock signal in the master system;

a communication apparatus that is adapted to communicate the master clock signal to the slave system so as to provide a communicated master clock signal;

a second generator that generates a time frame in the slave system, wherein the time frame is defined by a minimum time and a maximum time;

a third generator that generates a slave clock signal based on the communicated master clock signal, wherein a phase of the slave clock signal corresponds to an actual time;

a processor that determines if the slave clock signal is in the time frame, and that determines if the actual time is no greater than the minimum time if the slave clock signal is not in the time frame; and

a regulator that regulates the slave clock signal, if it is not in the time frame, by phase shifting the slave clock signal so that it occurs after the minimum time and before the maximum time in the time frame.

37. A system for synchronizing a slave system and a master system, the system comprising:

means for providing a master clock signal in the master system;

means for communicating the master clock signal to the slave system so as to provide a communicated master clock signal;

means for providing a time frame in the slave system, wherein the time frame is defined by a minimum time and a maximum time;

means for providing a slave clock signal based on the communicated master clock signal, wherein a phase of the slave clock signal corresponds to an actual time;

means for determining if the slave clock signal is in the time frame, and for determining if the actual time is no greater than the minimum time if the slave clock signal is not in the time frame; and

means for regulating the slave clock signal, if it is not in the time frame, by phase shifting the slave clock signal so that it occurs after the minimum time and before the maximum time in the time frame.