Memory system having error monitoring apparatus for multi-bit errors

• US 6,539,504 B1
• Filed: 02/01/1999
• Issued: 03/25/2003
• Est. Priority Date: 08/30/1996
• Status: Expired due to Fees

• Current Assignee: Siemens AG
• Original Assignee: Siemens AG
• Inventors: Knefel, Hans-Werner
• Primary Examiner(s): Ton, David
• Application Number:
  US09/230,757
• Time in Patent Office: 1,513 Days
• Field of Search: 714/762, 714/820, 714/718, 714/766, 714/763, 714/764, 365/201, 370/359, 370/360
• US Class Current: 714/718
• CPC Class Codes: G06F 11/1016 Error in accessing a memory location, i.e. addressing error
• CPC Class Codes: G06F 11/1028 Adjacent errors, e.g. error in n-bit (n>1) wide storage units, i.e. package error
• CPC Class Codes: G11B 20/1833 by adding special lists or symbols to the coded information G11B20/1806, G11B20/1866 take precedence

Abstract

The data contents of memory systems are mostly safeguarded via an EDC method. The memory system is structured such that the recognizability of multi-bit errors is improved considerably by the EDC method.

Claims

1. A memory system, comprising:

a memory in which memory words are stored that respectively have a data word and a control word, the memory having

a) two memory units, wherein a data word segment and a control word segment are respectively stored together in each memory unit, and

b) two error monitoring apparatuses that carry out an error monitoring of the memory word for multi-bit errors based on the control word;

a memory control unit for controlling the memory, the memory control unit having an additional two error monitoring apparatuses for error monitoring between the memory control unit and the memory; and

a doubled line structure between the memory control unit and the memory for doubled transfer of the memory words between the memory control unit and the memory, wherein the doubled line structure between the memory and the memory control unit is partially cross-connected such that one of the two segments of each data word being transferred is cross-connected.

2. The memory system of claim 1, wherein during a write operation, error monitoring is first carried out in the error monitoring apparatuses in the memory control unit before the data word to be written is forwarded to the memory units, and is then carried out a second time in the error monitoring apparatuses in memory before writing the data word.

3. The memory system of claim 1, wherein during a read operation, error monitoring first carried out in the error monitoring apparatuses in memory as the data word is read, and is then carried out a second time in the error monitoring apparatuses in the memory control unit.

4. A memory system, comprising:

a memory in which memory words are stored that respectively have a data word and a control word;

a memory having two memory units, a segment of the data word together with a segment of the control word being respectively stored in each memory unit;

the memory having two error monitoring apparatus that carry out an error monitoring of the memory word based on the control word;

a memory control unit for controlling the memory, the memory control unit also having two error monitoring apparatus for error monitoring between the memory control unit and the memory;

a doubled line structure between the memory control unit and the memory for doubled transfer of the memory words between the memory control unit and the memory;

the doubled line structure between the memory and the memory control unit being partially cross-connected such that one of two segments of the data word is cross-connected; and

the error monitoring apparatus carrying out the error monitoring such that the error monitoring apparatus produce a respective control word as a predetermined formation rule, using a coding unit, from a memory word to be monitored, compare bits of the respective control word with K-bits contained in the memory word, and, given inequality, infer a type of error from a pattern of equal and unequal K-bits, and the predetermined formation rule being selected such that given a one-bit error, the comparison yields an odd number of unequal K-bits so that an even number of unequal K-bits respectively contribute to the odd number of unequal K-bits from segments of the control word that are not stored together with a segment of the data word in which the one-bit error is present.

5. The monitoring system according to claim 4 wherein segment-by-segment partitioning of the data bits and K-bits to the two memory units of the memory system is selected such that an even number of K-bits are involved in an odd syndrome pattern based on a one-bit error, said K-bits not being stored together with a segment of the data word in which the one-bit error is present.

6. The monitoring system according to claim 4 wherein the pattern of equal and unequal K-bits is a syndrome pattern.