Method of designing, fabricating, testing and interconnecting an IC to external circuit nodes

• US 6,539,531 B2
• Filed: 12/01/2000
• Issued: 03/25/2003
• Est. Priority Date: 02/25/1999
• Status: Expired due to Fees

• Current Assignee: FormFactor Incorporated
• Original Assignee: FormFactor Incorporated
• Inventors: Long, John M., Miller, Charles A.
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): DO, THUAN V
• Application Number:
  US09/728,050
• Publication Number:
  US 20010000427A1
• Time in Patent Office: 844 Days
• Field of Search: 216/14, 716/8, 716/11-16, 716/6
• US Class Current: 716/106
• CPC Class Codes: H01L 2223/6611 Wire connections
• CPC Class Codes: H01L 2224/45014 Ribbon connectors, e.g. rectangular cross-section
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/4813 Connecting within a semiconductor or solid-state body, i.e. fly wire, bridge wire
• CPC Class Codes: H01L 2224/49113 the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/00015 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01022 Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01083 : Bismuth [Bi]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/30111 : matching

Abstract

A method for designing integrated circuits (ICs) and their interconnect systems includes IC component cells and interconnect component cells in a cell library. Each IC component cell provides both a physical and behavioral model of a component that may be incorporated into the IC while each interconnect component cell includes both a physical and behavioral model of a separate internal or external component of an interconnect system that may link the IC to external nodes. Both the IC and its interconnect systems are designed by selecting and specifying interconnections between component cells included in the cell library. Interconnect systems are flexibily designed to act like filters tuned to optimize desired frequency response characteristics. Behavior models of the IC and its interconnect systems, based on the behavior models of their selected component, are subjected to simulation and verification tools to determine whether the IC and its interconnect systems meet various performance criteria and constraints. The structural models of the interconnect systems developed during the design process guide subsequent fabrication of interconnect systems for both the IC'"'"'s intended testing and operating environments.

Claims

1. A method for designing, fabricating, testing and interconnecting an integrated circuit (IC) to external circuit nodes, the method comprising the steps of:

a. providing a cell library including a plurality of component cells and a plurality of interconnect component cells,

wherein each component cell corresponds to a separate IC component, and includes a structural model and a behavior model of its corresponding IC component, the structural model describing a layout of the corresponding IC component within the IC,

wherein each interconnect component cell corresponds to a separate component of an interconnect system forming a signal path between at least one internal circuit node of the IC and at least one external circuit node, wherein each interconnect component cell includes structural and behavioral models of its corresponding interconnect system component,

wherein at least one of said interconnect component cells corresponds to a interconnect system component that is external to said IC, wherein the structural model of each interconnect component residing within the IC describes its layout within the IC; and

b. selecting IC components to be included in said IC and selecting components of a plurality of interconnect systems to provide signal paths between said IC and an external circuit node by selecting corresponding ones of said plurality of component cells and interconnect component cells.

2. The method in accordance with claim 1 further comprising the steps of:

c. creating a behavioral model of said IC communicating via at least one of said plurality of interconnect systems selected based on behavioral models included in one of said interconnect component cells selected at step b, and

d. employing said behavioral model created at step c to simulate a behavior of said IC when communicating with one of said external nodes via said at least one interconnect system.

3. The method in accordance with claim 2 further comprising the steps of:

e. generating an IC structural model based on IC component structural models and interconnect system structural models included in the component cells and interconnect component cells selected at step b, and

f. fabricating said IC on a semiconductor wafer in accordance with said IC structural model.

4. The method in accordance with claim 3 further comprising the steps of:

g. linking said IC fabricated on said semiconductor wafer at step f to an integrated circuit tester through conductive paths; and

h. employing said integrated circuit tester to test behavior of said IC.

5. The method in accordance with claim 4 further comprising the steps of:

i. fabricating portions of the interconnect systems selected at step b that are external to said IC in accordance with specifications included in interconnect component cells selected at step b; and

j. linking said IC to external circuit nodes via the interconnect system portions fabricated at step i.

6. The method in accordance with claim 3

wherein at least one interconnect component cell selected at step b corresponds to a spring contact and includes a description of the spring contact, wherein the method further comprises the step of:

g. fabricating the spring contact on said IC in accordance with the description of the spring contact included in its corresponding interconnect component cell.

7. The method in accordance with claim 6 further comprising the steps of:

h. linking said IC fabricated on said semiconductor wafer to an integrated circuit tester via said spring contact fabricated at step g; and

i. employing said integrated circuit tester to test behavior of said IC using a signal conveyed via said spring contact fabricated at step g.

8. The method in accordance with claim 7 further comprising the step of:

j. linking said IC to an external circuit node via said spring contact fabricated at step g.

9. The method in accordance with claim 2

wherein the components of at least one interconnect system selected at step b comprise:

a driver internal to said IC for generating a first signal to be conveyed by the interconnect system in response to a second signal produced at an internal node of the IC,

a receiver external to said IC for receiving said first signal, and

conductive means internal and external to said IC for conveying said first signal from said driver to said receiver,

wherein the behavioral model of said IC communicating via said at least one interconnect system models a manner in which impedances of said driver, said conductive means, and said receiver affect said first signal.

10. The method in accordance with claim 9

wherein said at least one interconnect system further comprises an electrostatic discharge protection device, and

wherein the behavioral model of said IC communicating via said at least one interconnect system also models a manner in which an impedance of said electrostatic protection device affects said first signal.

11. The method in accordance with claim 1 wherein at least two of said plurality of said interconnect systems selected at step b have substantially differing maximum current-carrying capacities.

12. The method in accordance with claim 1 wherein at least two of said plurality of interconnect systems selected at step b include spring contacts having substantially differing maximum current-carrying capacities.

13. The method in accordance with claim 1 wherein at least two of said plurality of interconnect systems selected at step b include bond wires having substantially differing maximum current-carrying capacities.

14. The method in accordance with claim 1 wherein at least two of said plurality of interconnect systems selected at step b comprise spring contacts of substantially differing dimensions.

15. The method in accordance with claim 1 wherein at least two of said plurality of said interconnect systems selected at step b have substantially differing frequency response characteristics.

16. The method in accordance with claim 15 wherein at least two of said plurality of said interconnect systems selected at step b have substantially differing frequency response characteristics.

17. A method for designing an integrated circuit (IC) having a plurality of terminals for transmitting signals to and receiving signals from external circuits and for designing a plurality of interconnect systems, each providing a complete signal path between one of said terminals and a circuit node external to said IC, the method comprising the steps of:

a. generating a hardware description language (HDL) description of the IC and said plurality of interconnect systems and descriptions of performance criteria and constraints for the IC and for the plurality of interconnect systems;

b. providing a cell library including IC component cells and interconnect component cells, wherein each IC component cell provides both a physical and behavioral model of a component that may be incorporated into the IC, wherein each interconnect component cell includes both a physical and behavioral model of a separate component of said interconnect systems, including components both internal and external to the IC;

c. employing synthesis tools to process said HDL description thereby producing a netlist design of said IC and said plurality of interconnect systems by selecting IC and interconnect component cells included in the cell library and by specifying a manner in which corresponding IC and interconnect system components are to be connected to one another.

18. The method in accordance with claim 17 further comprising the steps of:

d. simulating behavior of the IC and its interconnect systems based on the netlist design produced at step c and on behavioral models provided by IC and interconnect component cells included in said cell library to estimate how well an IC and its interconnect systems produced in accordance with the netlist design will satisfy said performance criteria and constraints.

19. The method in accordance with claim 18 further comprising the step of

e. generating a floorplan, a placement plan and a routing plan for said IC based on said netlist design and on the physical models provided by IC and interconnect component cells included in said cell library.

20. The method in accordance with claim 19 further comprising the step of

f. generating a physical design of portions of said interconnect systems that are external to said IC based on said netlist design and on the physical models provided by IC and interconnect component cells included in said cell library.

21. The method in accordance with claim 20 further comprising the step of

g. simulating behavior of the IC and its interconnect systems based on the floorplan, placement plan and routing plan generated at step e and on the physical design of portions of said interconnect systems that are external to said IC generated at step f and on behavioral models provided by IC and interconnect component cells included in said cell library to estimate how well an IC and its interconnect systems produced in accordance with said floorplan, placement plan, and routing plan and said physical design will satisfy said performance criteria and constraints.

22. The method in accordance with claim 21 further comprising the step of

h. fabricating said IC in accordance with the floorplan, placement plan and routing plan generated at step e.

23. The method in accordance with claim 22 further comprising the step of

i. fabricating said portions of said interconnect systems that are external to said IC in accordance with the physical design generated at step f.

24. The method in accordance with claim 22 wherein each said interconnect system includes a spring contact and other portions external to said IC, and wherein the method further comprises the step of:

i. fabricating said spring contacts on a surface of said IC in accordance with the physical design generated at step f.

25. The method in accordance with claim 24 further comprising the step of

j. fabricating other portions of at least two of said interconnect systems in accordance with the physical design generated at step f.

26. The method in accordance with claim 25 wherein said other portions of said interconnect systems include printed circuit board traces.

27. The method in accordance with claim 22 wherein said physical design generated at step f describes portions of first interconnect systems external to said IC that are to link said IC to an integrated circuit tester and portions of second interconnect systems that are to link said IC to said external circuits.

28. The method in accordance with claim 17 further comprising the steps of:

i. fabricating said portions of said first interconnect systems in accordance with the physical design generated at step f, and

j. linking said IC fabricated at step h to an integrated circuit tester via said portions of said first interconnect systems fabricated at step i.

29. The method in accordance with claim 28 further comprising the steps of

k. fabricating said portions of said second interconnect systems in accordance with the physical design generated at step f, and

l. linking said IC fabricated at step h to said external circuits via said portions of said first interconnect systems fabricated at step i.